| /Linux-v5.10/drivers/clk/ti/ |
| D | composite.c | 124 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); in _register_composite() local
133 if (!cclk->comp_nodes[i]) in _register_composite()
136 comp = _lookup_component(cclk->comp_nodes[i]); in _register_composite()
139 cclk->comp_nodes[i]->name, node); in _register_composite()
146 if (cclk->comp_clks[comp->type] != NULL) { in _register_composite()
152 cclk->comp_clks[comp->type] = comp; in _register_composite()
155 cclk->comp_nodes[i] = NULL; in _register_composite()
160 comp = cclk->comp_clks[i]; in _register_composite()
177 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), in _register_composite()
179 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER), in _register_composite()
[all …]
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| /Linux-v5.10/drivers/clk/sprd/ |
| D | common.c | 28 struct sprd_clk_common *cclk; in sprd_clk_set_regmap() local
31 cclk = desc->clk_clks[i]; in sprd_clk_set_regmap()
32 if (!cclk) in sprd_clk_set_regmap()
35 cclk->regmap = regmap; in sprd_clk_set_regmap()
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| /Linux-v5.10/sound/soc/samsung/ |
| D | pcm.c | 113 * @cclk: the SCLK_AUDIO (audio-bus) clock pointer
128 struct clk *cclk; member
288 clk = pcm->cclk; in s3c_pcm_hw_params()
421 if (clk_get_rate(pcm->cclk) != freq) in s3c_pcm_set_sysclk()
422 clk_set_rate(pcm->cclk, freq); in s3c_pcm_set_sysclk()
520 pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus"); in s3c_pcm_dev_probe()
521 if (IS_ERR(pcm->cclk)) { in s3c_pcm_dev_probe()
523 return PTR_ERR(pcm->cclk); in s3c_pcm_dev_probe()
525 ret = clk_prepare_enable(pcm->cclk); in s3c_pcm_dev_probe()
578 clk_disable_unprepare(pcm->cclk); in s3c_pcm_dev_probe()
[all …]
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| /Linux-v5.10/drivers/clk/sunxi-ng/ |
| D | ccu_common.c | 89 struct ccu_common *cclk = desc->ccu_clks[i]; in sunxi_ccu_probe() local
91 if (!cclk) in sunxi_ccu_probe()
94 cclk->base = reg; in sunxi_ccu_probe()
95 cclk->lock = &ccu_lock; in sunxi_ccu_probe()
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| /Linux-v5.10/drivers/iio/adc/ |
| D | ti-adc12138.c | 41 struct clk *cclk; member
48 /* The number of cclk periods for the S/H's acquisition time */
437 adc->cclk = devm_clk_get(&spi->dev, NULL); in adc12138_probe()
438 if (IS_ERR(adc->cclk)) in adc12138_probe()
439 return PTR_ERR(adc->cclk); in adc12138_probe()
461 ret = clk_prepare_enable(adc->cclk); in adc12138_probe()
499 clk_disable_unprepare(adc->cclk); in adc12138_probe()
514 clk_disable_unprepare(adc->cclk); in adc12138_remove()
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| /Linux-v5.10/drivers/spi/ |
| D | spi-qup.c | 128 struct clk *cclk; /* core clock */ member
672 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
998 struct clk *iclk, *cclk; in spi_qup_probe() local
1016 cclk = devm_clk_get(dev, "core"); in spi_qup_probe()
1017 if (IS_ERR(cclk)) in spi_qup_probe()
1018 return PTR_ERR(cclk); in spi_qup_probe()
1033 ret = clk_prepare_enable(cclk); in spi_qup_probe()
1041 clk_disable_unprepare(cclk); in spi_qup_probe()
1048 clk_disable_unprepare(cclk); in spi_qup_probe()
1078 controller->cclk = cclk; in spi_qup_probe()
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | renesas,h8300-div-clock.txt | 18 cclk: cclk {
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| /Linux-v5.10/drivers/clk/rockchip/ |
| D | clk-cpu.c | 254 struct clk *clk, *cclk; in rockchip_clk_register_cpuclk() local
327 cclk = clk_register(NULL, &cpuclk->hw); in rockchip_clk_register_cpuclk()
328 if (IS_ERR(cclk)) { in rockchip_clk_register_cpuclk()
330 ret = PTR_ERR(cclk); in rockchip_clk_register_cpuclk()
334 return cclk; in rockchip_clk_register_cpuclk()
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | stm32mp153.dtsi | 34 clock-names = "hclk", "cclk";
47 clock-names = "hclk", "cclk";
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| D | dra76x.dtsi | 36 clock-names = "hclk", "cclk";
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| /Linux-v5.10/drivers/net/can/m_can/ |
| D | m_can_platform.c | 107 mcan_class->can.clock.freq = clk_get_rate(mcan_class->cclk); in m_can_plat_probe()
154 clk_disable_unprepare(mcan_class->cclk); in m_can_runtime_suspend()
170 err = clk_prepare_enable(mcan_class->cclk); in m_can_runtime_resume()
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| D | m_can.h | 78 struct clk *cclk; member
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| D | tcan4x5x.c | 459 if (IS_ERR(mcan_class->cclk)) { in tcan4x5x_can_probe()
463 freq = clk_get_rate(mcan_class->cclk); in tcan4x5x_can_probe()
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| /Linux-v5.10/drivers/staging/gs_fpgaboot/ |
| D | io.c | 23 /* Assert and Deassert CCLK */
49 /* Serialize byte and clock each bit on target's DIN and CCLK pins */
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| /Linux-v5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | ti,adc12138.yaml | 51 For less ADC accuracy and/or slower CCLK frequencies this value may be
79 clocks = <&cclk>;
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| /Linux-v5.10/drivers/mmc/host/ |
| D | mmci_stm32_sdmmc.c | 204 * cclk = mclk / (2 * clkdiv) in mmci_sdmmc_set_clkreg()
210 host->cclk = host->mclk; in mmci_sdmmc_set_clkreg()
215 host->cclk = host->mclk / (2 * clk); in mmci_sdmmc_set_clkreg()
224 host->cclk = host->mclk / (2 * clk); in mmci_sdmmc_set_clkreg()
229 host->mmc->actual_clock = host->cclk; in mmci_sdmmc_set_clkreg()
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| D | mmci.c | 358 if (host->cclk < 25000000) in mmci_reg_delay()
408 /* Make sure cclk reflects the current calculated clock */ in mmci_set_clkreg()
409 host->cclk = 0; in mmci_set_clkreg()
413 host->cclk = host->mclk; in mmci_set_clkreg()
418 host->cclk = host->mclk; in mmci_set_clkreg()
429 host->cclk = host->mclk / (clk + 2); in mmci_set_clkreg()
438 host->cclk = host->mclk / (2 * (clk + 1)); in mmci_set_clkreg()
448 host->mmc->actual_clock = host->cclk; in mmci_set_clkreg()
1142 clks = (unsigned long long)data->timeout_ns * host->cclk; in mmci_start_data()
1244 clks = (unsigned long long)cmd->busy_timeout * host->cclk; in mmci_start_command()
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| /Linux-v5.10/Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 50 - const: cclk
135 clock-names = "hclk", "cclk";
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| /Linux-v5.10/drivers/net/ethernet/chelsio/cxgb4vf/ |
| D | t4vf_common.h | 198 u32 cclk; /* Core Clock (KHz) */ member
311 return adapter->params.vpd.cclk / 1000; in core_ticks_per_usec()
317 return (us * adapter->params.vpd.cclk) / 1000; in us_to_core_ticks()
323 return (ticks * 1000) / adapter->params.vpd.cclk; in core_ticks_to_us()
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| /Linux-v5.10/drivers/fpga/ |
| D | xilinx-spi.c | 164 dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); in xilinx_spi_apply_cclk_cycles()
181 * before giving up and we apply 8 extra CCLK cycles in all cases. in xilinx_spi_write_complete()
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| /Linux-v5.10/drivers/scsi/csiostor/ |
| D | csio_hw.h | 265 uint32_t cclk; member
582 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk; in csio_core_ticks_to_us()
588 return (us * hw->vpd.cclk) / 1000; in csio_us_to_core_ticks()
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| /Linux-v5.10/drivers/clk/tegra/ |
| D | Makefile | 16 obj-y += clk-tegra-super-cclk.o
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| D | clk-tegra-super-cclk.c | 69 * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. in cclk_super_determine_rate()
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| /Linux-v5.10/drivers/clk/ingenic/ |
| D | jz4770-cgu.c | 152 "cclk", CGU_CLK_DIV,
191 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
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| /Linux-v5.10/arch/arm/mach-sa1100/include/mach/ |
| D | assabet.h | 97 #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
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