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/Linux-v5.10/drivers/clk/baikal-t1/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
31 bool "Baikal-T1 CCU Dividers support"
37 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
Dccu-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU PLL interface driver
10 #include <linux/clk-provider.h>
17 * struct ccu_pll_init_data - CCU PLL initialization data
22 * @sys_regs: Baikal-T1 System Controller registers map.
37 * struct ccu_pll - CCU PLL descriptor
42 * @sys_regs: Baikal-T1 System Controller registers map.
43 * @lock: PLL state change spin-lock.
57 return pll ? &pll->hw : NULL; in ccu_pll_get_clk_hw()
Dccu-div.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
22 * @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
31 * enum ccu_div_type - CCU Divider types
43 * struct ccu_div_init_data - CCU Divider initialization data
48 * @sys_regs: Baikal-T1 System Controller registers map.
73 * struct ccu_div - CCU Divider descriptor
77 * @sys_regs: Baikal-T1 System Controller registers map.
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Dclk-ccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 * Baikal-T1 CCU PLL clocks driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
17 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/bt1-ccu.h>
26 #include "ccu-pll.h"
56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
57 * DDR controller AXI-bus clocks. If they are gated the system will be
59 * of the corresponding subsystems. So until we aren't ready to re-initialize
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Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
17 #include <linux/clk-provider.h>
18 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
27 #include <dt-bindings/reset/bt1-ccu.h>
29 #include "ccu-div.h"
128 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
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/Linux-v5.10/Documentation/devicetree/bindings/memory-controllers/
Dbaikal,bt1-l2-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
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/Linux-v5.10/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
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Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
22 - $ref: /schemas/simple-bus.yaml#
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/Linux-v5.10/Documentation/devicetree/bindings/hwmon/
Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
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/Linux-v5.10/drivers/hwmon/
Dbt1-pvt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 Process, Voltage, Temperature sensor driver
17 /* Baikal-T1 PVT registers and their bitfields */
61 * PVT sensors-related limits and default values
73 * when one is determined for Baikal-T1 SoC).
84 #define PVT_TEMP_MIN -48380L
105 * enum pvt_sensor_type - Baikal-T1 PVT sensor types (correspond to each PVT
110 * @PVT_LVT: PVT Low-Voltage threshold sensor.
111 * @PVT_HVT: PVT High-Voltage threshold sensor.
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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
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Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
[all …]
/Linux-v5.10/drivers/memory/
Dbt1-l2-ctl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
42 LP-DDR memories.
53 Used to configure the EBI (external bus interface) when the device-
70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
77 tags and way-select latencies of RAM access. This driver provides a
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/Linux-v5.10/drivers/mtd/maps/
Dphysmap-bt1-rom.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 Physically Mapped Internal ROM driver
22 #include "physmap-bt1-rom.h"
25 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
26 * We have to take this into account when implementing the data read-methods.
27 * Note there is no need in bothering with endianness, since both Baikal-T1
33 void __iomem *src = map->virt + ofs; in bt1_rom_map_read()
40 data = readl_relaxed(src - shift); in bt1_rom_map_read()
48 shift = 4 - shift; in bt1_rom_map_read()
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/Linux-v5.10/drivers/spi/
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
60 * mapped flash memory bounds and the operation is read-only. in dw_spi_bt1_dirmap_create()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
111 supports spi-mem interface.
181 this code to manage the per-word or per-transfer accesses to the
211 Flash over 1/2/4-bit wide bus. Enable this option if you have a
219 This enables dedicated general purpose SPI/Microwire1-compatible
220 master mode interface (SSI1) for CLPS711X-based CPUs.
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/Linux-v5.10/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: "spi-controller.yaml#"
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/Linux-v5.10/drivers/bus/
Dbt1-axi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
38 * @sys_regs: Baikal-T1 System Controller registers map.
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
66 dev_crit_ratelimited(axi->dev, in bt1_axi_isr()
67 "AXI-bus fault %d: %s at 0x%x%08x\n", in bt1_axi_isr()
68 atomic_inc_return(&axi->count), in bt1_axi_isr()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
103 cores. This bus is for per-CPU tightly coupled devices such as the
[all …]
Dbt1-apb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 APB-bus driver
38 * struct bt1_apb - Baikal-T1 APB EHB private data
41 * @res: No-device error injection memory region.
43 * @rate: APB-bus reference clock rate.
44 * @pclk: APB-reference clock.
75 do_div(timeout, apb->rate); in bt1_apb_n_to_timeout_us()
84 u64 n = (u64)timeout * apb->rate; in bt1_apb_timeout_to_n_us()
97 regmap_read(apb->regs, APB_EHB_ADDR, &addr); in bt1_apb_isr()
[all …]
/Linux-v5.10/include/dt-bindings/reset/
Dbt1-ccu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU reset indices
/Linux-v5.10/include/dt-bindings/clock/
Dbt1-ccu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU clock indices
/Linux-v5.10/Documentation/hwmon/
Dbt1-pvt.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 Kernel driver bt1-pvt
8 * Baikal-T1 PVT sensor (in SoC)
10 Prefix: 'bt1-pvt'
12 Addresses scanned: -
14 Datasheet: Provided by BAIKAL ELECTRONICS upon request and under NDA
21 -----------
24 embedded into Baikal-T1 process, voltage and temperature sensors. PVT IP-core
29 compile-time configurable due to the hardware interface implementation
40 in alarm-less configuration the data conversion is performed by the driver
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/Linux-v5.10/Documentation/devicetree/bindings/i2c/
Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
29 const: snps,designware-i2c
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