Searched full:armv7 (Results 1 – 25 of 227) sorted by relevance
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/Linux-v6.1/arch/arm/mach-mmp/ |
D | Kconfig | 64 ARMv7 architecture. 76 ARMv7 architecture. 88 ARMv7 architecture. 122 bool "Support MMP2 (ARMv7) platforms from device tree" 135 bool "Support MMP3 (ARMv7) platforms" 170 Select code specific to MMP2. MMP2 is ARMv7 compatible.
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/Linux-v6.1/Documentation/devicetree/bindings/arm/ |
D | pmu.yaml | 96 Indicates that the ARMv7 Secure Debug Enable Register 98 any setup required that is only possible in ARMv7 secure 99 state. If not present the ARMv7 SDER will not be touched, 103 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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/Linux-v6.1/Documentation/devicetree/bindings/timer/ |
D | arm,arch_timer.yaml | 26 - const: arm,armv7-timer 29 - arm,armv7-timer 33 - const: arm,armv7-timer 95 supported for 32-bit systems which follow the ARMv7 architected reset 120 "arm,armv7-timer";
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D | arm,arch_timer_mmio.yaml | 23 - arm,armv7-timer-mem 52 supported for 32-bit systems which follow the ARMv7 architected reset 101 compatible = "arm,armv7-timer-mem";
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/Linux-v6.1/arch/arm/mm/ |
D | Makefile | 37 AFLAGS_abort-ev7.o :=-Wa,-march=armv7-a 53 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a 54 AFLAGS_cache-v7m.o :=-Wa,-march=armv7-m 76 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a 105 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
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D | proc-v7m.S | 8 * This is the "shell" of the ARMv7-M processor support. 104 * This should be able to cover all ARMv7-M cores. 178 string cpu_v7m_name "ARMv7-M" 247 * Match any ARMv7-M processor core.
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D | cache-tauros2.c | 243 * not complying with all of the other ARMv7 requirements), in tauros2_internal_init() 251 * When Tauros2 is used in an ARMv7 system, the L2 in tauros2_internal_init() 254 * ARMv7 spec to contain fine-grained cache control bits). in tauros2_internal_init() 262 mode = "ARMv7"; in tauros2_internal_init()
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D | Kconfig | 406 # ARMv7 670 Say Y if you have an ARMv7 processor supporting the LPAE page 725 ARMv7 multiprocessing extensions introduce the ability to disable 774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 905 run on ARMv4 through to ARMv7 without modification. 1122 provide DMA coherent memory. With the advent of ARMv7, mapping 1134 On some of the beefier ARMv7-M machines (with DMA and write
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/Linux-v6.1/Documentation/arm/ |
D | marvell.rst | 131 Sheeva ARMv7 compatible PJ4B 150 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP 302 Sheeva ARMv7 compatible Quad-core PJ4C 325 ARMv7 compatible 362 - Core: ARMv7 compatible Sheeva PJ4 core 400 - Core: ARMv7 compatible Sheeva PJ4 88sv581x core 404 - Core: Dual-core ARMv7 compatible Sheeva PJ4C core 407 - Core: ARMv7 compatible Sheeva PJ4 core 410 - Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core 413 - Core: quad-core ARMv7 Cortex-A7 [all …]
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/Linux-v6.1/arch/arm/mach-mstar/ |
D | Kconfig | 2 bool "MStar/Sigmastar Armv7 SoC Support" 12 based on Armv7 cores like the Cortex A7 and share the same
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D | mstarv7.c | 3 * Device Tree support for MStar/Sigmastar Armv7 SoCs 125 DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
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/Linux-v6.1/arch/arm/mach-imx/ |
D | Makefile | 37 AFLAGS_headsmp.o :=-Wa,-march=armv7-a 51 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a 56 AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
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/Linux-v6.1/arch/arm/mach-stm32/ |
D | Kconfig | 42 endif # ARMv7-M 59 endif # ARMv7-A
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/Linux-v6.1/arch/arm/common/ |
D | Makefile | 16 AFLAGS_mcpm_head.o := -march=armv7-a 17 AFLAGS_vlock.o := -march=armv7-a
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/Linux-v6.1/arch/arm/mach-mvebu/ |
D | Makefile | 4 AFLAGS_coherency_ll.o := -Wa,-march=armv7-a 5 CFLAGS_pmsu.o := -march=armv7-a
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/Linux-v6.1/Documentation/devicetree/bindings/arm/mstar/ |
D | mstar,smpctrl.yaml | 8 title: MStar/SigmaStar Armv7 SoC SMP control registers 14 MStar/SigmaStar's Armv7 SoCs that have more than one processor
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D | mstar,l3bridge.yaml | 8 title: MStar/SigmaStar Armv7 SoC l3bridge 14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
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/Linux-v6.1/arch/arm/mach-versatile/ |
D | Makefile | 20 CFLAGS_dcscb.o += -march=armv7-a 25 CFLAGS_tc2_pm.o += -march=armv7-a
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/Linux-v6.1/Documentation/trace/coresight/ |
D | coresight-cpu-debug.rst | 49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different 53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the 54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU 56 detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
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/Linux-v6.1/drivers/soc/samsung/ |
D | Kconfig | 12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST 48 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
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/Linux-v6.1/arch/arm/mach-at91/ |
D | Kconfig | 73 bool "ARMv7 based Microchip LAN966 SoC family" 79 This enables support for ARMv7 based Microchip LAN966 SoC family.
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/Linux-v6.1/arch/arm/kernel/ |
D | entry-v7m.S | 7 * Low-level vector interface routines for the ARMv7-M architecture 101 * Register switch for ARMv7-M processors.
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D | Makefile | 73 CFLAGS_swp_emulate.o := -Wa,-march=armv7-a 102 AFLAGS_hyp-stub.o :=-Wa,-march=armv7-a
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/Linux-v6.1/arch/arm64/kernel/ |
D | compat_alignment.c | 39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ 75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd() 229 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. 230 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
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/Linux-v6.1/arch/arm/mach-npcm/ |
D | Makefile | 2 AFLAGS_headsmp.o += -march=armv7-a
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