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Searched full:auxclk (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.10/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-ivi-audio.yaml23 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
29 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
30 | |-> MCASP0_AUXCLK ---> McASP0.auxclk
36 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
37 | |-> MCASP0_AUXCLK ---> McASP0.auxclk
73 - description: AUXCLK clock for McASP used by CPB audio
74 - description: Parent for CPB_McASP auxclk (for 48KHz)
75 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: AUXCLK clock for McASP used by IVI audio
80 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
Dti,j721e-cpb-audio.yaml18 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
23 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
27 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
32 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
83 - description: AUXCLK clock for McASP used by CPB audio
84 - description: Parent for CPB_McASP auxclk (for 48KHz)
85 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
92 - const: cpb-mcasp-auxclk
93 - const: cpb-mcasp-auxclk-48000
94 - const: cpb-mcasp-auxclk-44100
[all …]
Ddavinci-mcasp-audio.txt47 - auxclk-fs-ratio: When McASP is bus master indicates the ratio between AUCLK
49 AUCLK rate = auxclk-fs-ratio * FS rate
/Linux-v5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt40 auxclk
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
71 pll0_auxclk: auxclk {
Dda8xx-cfgchip.txt16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
63 clock-names = "fck", "usb_refclkin", "auxclk";
/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts81 clock-names = "cpb-mcasp-auxclk",
82 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
551 auxclk-fs-ratio = <256>;
/Linux-v5.10/drivers/clk/davinci/
Dpll.c391 * and will be the parent clock to the AUXCLK, SYSCLKBP and in davinci_pll_clk_register()
538 * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
811 child = of_get_child_by_name(node, "auxclk"); in of_davinci_pll_init()
/Linux-v5.10/sound/soc/ti/
Ddavinci-mcasp.h303 #define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */
Dj721e-evm.c636 ret = j721e_get_clocks(priv->dev, &domain->mcasp, "cpb-mcasp-auxclk"); in j721e_soc_probe_cpb()
738 ret = j721e_get_clocks(priv->dev, &domain->mcasp, "ivi-mcasp-auxclk"); in j721e_soc_probe_ivi()
Ddavinci-mcasp.c690 /* Select AUXCLK as HCLK */ in davinci_mcasp_set_sysclk()
697 * the same clock - coming via AUXCLK. in davinci_mcasp_set_sysclk()
2122 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val); in davinci_mcasp_get_dt_params()
/Linux-v5.10/arch/arm/boot/dts/
Dda850.dtsi147 pll0_auxclk: auxclk {
392 clock-names = "fck", "usb_refclkin", "auxclk";
/Linux-v5.10/drivers/gpu/drm/msm/dp/
Ddp_catalog.c268 pr_info("AUXCLK regs\n"); in dp_catalog_dump_regs()
/Linux-v5.10/drivers/tty/
Dsynclink_gt.c3902 * 01 auxclk enable (0 = disable) in enable_loopback()
4185 * 01 0 = auxclk disabled in async_mode()
4373 * 01 auxclk enable in sync_mode()
Dsynclinkmp.c4435 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out in async_mode()
4611 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out in hdlc_mode()
/Linux-v5.10/drivers/char/pcmcia/
Dsynclink_cs.c2923 /* channel B RTS is used to enable AUXCLK driver on SP505 */ in enable_auxclk()
2983 /* if auxclk not enabled, set internal BRG so in enable_auxclk()