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/Linux-v5.15/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
12 bool "Allwinner sunxi 64-bit SoC Family"
21 This enables support for Allwinner sunxi based SoCs like the A64.
34 This enables support for Apple's in-house ARM SoC family, starting
57 BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be
66 This enables support for Broadcom iProc based SoCs
83 bool "Broadcom Set-Top-Box SoCs"
90 This enables support for Broadcom's ARMv8 Set Top Box SoCs
93 bool "ARMv8 based Samsung Exynos SoC family"
104 This enables support for ARMv8 based Samsung Exynos SoC family.
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
177 if $(cc-option,-fpatchable-function-entry=2)
225 ARM 64-bit (AArch64) Linux support.
257 # VA_BITS - PAGE_SHIFT - 3
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
363 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
377 data cache clean-and-invalidate.
385 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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/Linux-v5.15/arch/arm/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
13 tristate "SHA1 digest algorithm (ARM-asm)"
17 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
27 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
37 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
38 using special ARMv8 Crypto Extensions.
41 tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
46 SHA-256 secure hash standard (DFIPS 180-2) implemented
47 using special ARMv8 Crypto Extensions.
50 tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
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Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
5 * Copyright (C) 2015 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
11 .arch armv8-a
12 .fpu crypto-neon-fp-armv8
100 * This implementation of 64x64 -> 128 bit polynomial multiplication
101 * using vmull.p8 instructions (8x8 -> 16) is taken from the paper
104 * Ricardo Dahab (https://hal.inria.fr/hal-01506572)
106 * It has been slightly tweaked for in-order performance, and to allow
158 // PMULL (64x64->128) based reduction for CPUs that can do
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/Linux-v5.15/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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/Linux-v5.15/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
70 based on the Stream ID of the corresponding master.
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/Linux-v5.15/drivers/soc/samsung/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 # There is no need to enable these drivers for ARMv8
12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
29 # There is no need to enable these drivers for ARMv8
31 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
46 Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
56 Note, this currently only works for S3C64XX based SMDK boards.
71 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
83 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
/Linux-v5.15/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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Dcoresight-cpu-debug.txt3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
8 debug module provides sample-based profiling extension, which can be used
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
22 - clock-names : the name of the clock referenced by the code. Since we are
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
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Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
51 On ARM 11 MPcore based systems this property is
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
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/Linux-v5.15/drivers/soc/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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/Linux-v5.15/Documentation/arm64/
Darm-acpi.rst2 ACPI on ARMv8 Servers
5 ACPI can be used for ARMv8 general purpose servers designed to follow
11 The ARMv8 kernel implements the reduced hardware model of ACPI version
17 If an ARMv8 system does not meet the requirements of the SBSA and SBBR,
22 industry-standard ARMv8 servers, they also apply to more than one operating
24 ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of
29 ----------------
32 exist in Linux for describing non-enumerable hardware, after all. In this
34 reasoning behind ACPI on ARMv8 servers. Actually, we snitch a good portion
39 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
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Dmemory-tagging-extension.rst8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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Dpointer-authentication.rst7 Date: 2017-07-19
14 ---------------------
16 The ARMv8.3 Pointer Authentication extension adds primitives that can be
27 of high-order bits of the pointer, which varies dependent on the
36 The extension provides five separate keys to generate PACs - two for
42 -------------
56 Recent versions of GCC can compile code with APIAKey-based return
57 address protection when passed the -msign-return-address option. This
58 uses instructions in the HINT space (unless -march=armv8.3-a or higher
70 ---------
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Dacpi_object_usage.rst16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IBFT,
24 - Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx,
28 Table Usage for ARMv8 Linux
47 Optional, not currently supported, with no real use-case for an
55 time as ARM-compatible hardware is available, and the specification
123 UEFI-based; if it is UEFI-based, this table may be supplied. When this
139 the hardware reduced profile, and only 64-bit address fields will
156 filled in properly - that the PSCI_COMPLIANT flag is set and that
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/Linux-v5.15/drivers/clk/samsung/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
73 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
100 Build the s3c2410 clock driver based on the common clock framework.
107 Temporary symbol to build the dclk driver based on the common clock
/Linux-v5.15/lib/
DKconfig.kasan1 # SPDX-License-Identifier: GPL-2.0-only
23 def_bool $(cc-option, -fsanitize=kernel-address)
26 def_bool $(cc-option, -fsanitize=kernel-hwaddress)
43 Enables KASAN (KernelAddressSANitizer) - runtime memory debugger,
44 designed to find out-of-bounds accesses and use-after-free bugs.
45 See Documentation/dev-tools/kasan.rst for details.
56 2. software tag-based KASAN (arm64 only, based on software
59 3. hardware tag-based KASAN (arm64 only, based on hardware
77 but detection of out-of-bounds accesses for global variables is
88 bool "Software tag-based mode"
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/Linux-v5.15/arch/arm64/kvm/hyp/
Dexception.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012,2013 - ARM Ltd
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
49 vcpu->arch.ctxt.spsr_abt = val; in __vcpu_write_spsr_abt()
57 vcpu->arch.ctxt.spsr_und = val; in __vcpu_write_spsr_und()
63 * The EL passed to this function *must* be a non-secure, privileged mode with
71 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
72 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
115 if (kvm_has_mte(vcpu->kvm)) in enter_exception64()
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/Linux-v5.15/Documentation/dev-tools/
Dkasan.rst5 --------
8 designed to find out-of-bound and use-after-free bugs. KASAN has three modes:
11 2. software tag-based KASAN (similar to userspace HWASan),
12 3. hardware tag-based KASAN (based on hardware memory tagging).
15 Software tag-based KASAN can be used for dogfood testing as it has a lower
16 memory overhead that allows using it with real workloads. Hardware tag-based
18 used in production. Either as an in-field memory bug detector or as a security
21 Software KASAN modes (#1 and #2) use compile-time instrumentation to insert
27 out-of-bounds accesses for global variables is only supported since Clang 11.
29 Software tag-based KASAN mode is only supported in Clang.
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/Linux-v5.15/arch/arm64/kernel/
Dperf_event.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARMv8 PMUv3 Performance Events handling code.
8 * This code is based heavily on the ARMv7 perf event code.
27 /* ARMv8 Cortex-A53 specific event types. */
30 /* ARMv8 Cavium ThunderX specific event types. */
38 * ARMv8 Architectural defined events, not all of these may
40 * be disabled at run-time based on the PMCEID registers.
164 return sprintf(page, "event=0x%04llx\n", pmu_attr->id); in armv8pmu_events_sysfs_show()
265 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && in armv8pmu_event_attr_is_visible()
266 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) in armv8pmu_event_attr_is_visible()
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/Linux-v5.15/drivers/hwtracing/coresight/
Dcoresight-cpu-debug.c1 // SPDX-License-Identifier: GPL-2.0
27 #include "coresight-priv.h"
64 * NOTE: armv8 and armv7 have different definition for the register,
67 * 0b0000 - Sample offset applies based on the instruction state, we
69 * 0b0001 - No offset applies.
70 * 0b0010 - No offset applies, but do not use in AArch32 mode
115 writel_relaxed(0x0, drvdata->base + EDOSLAR); in debug_os_unlock()
127 * - CPU power domain is powered off;
128 * - The OS Double Lock is locked;
135 if (!(drvdata->edprsr & EDPRSR_PU)) in debug_access_permitted()
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/Linux-v5.15/Documentation/arm/samsung/
Dbootloader-interface.rst10 and boot loaders on Samsung Exynos based boards. This is not a definition
14 In the document "boot loader" means any of following: U-boot, proprietary
15 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
19 1. Non-Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/Linux-v5.15/Documentation/admin-guide/kdump/
Dvmcoreinfo.rst11 section and used by user-space tools like crash and makedumpfile to
18 ------------------------
25 ---------
32 -----------
39 User-space tools can get the kernel name, host name, kernel release
43 ---------------------
49 ---------------
56 --------------
62 ------
69 --------------
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/Linux-v5.15/Documentation/arm/
Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181
18 - 88F5181L
19 - 88F5182
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 - 88F5281
26 …- Datasheet: https://web.archive.org/web/20131028144728/http://www.ocmodshop.com/images/reviews/ne…
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/Linux-v5.15/arch/arm64/include/asm/
Dtlbflush.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/tlbflush.h
5 * Copyright (C) 1999-2003 Russell King
68 * - 4KB : 1
69 * - 16KB : 2
70 * - 64KB : 3
91 * Level-based TLBI operations.
93 * When ARMv8.4-TTL exists, TLBI operations take an additional hint for
97 * perform a non-hinted invalidation.
99 * For Stage-2 invalidation, use the level values provided to that effect
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