Searched full:armv5 (Results 1 – 19 of 19) sorted by relevance
| /Linux-v5.10/Documentation/arm/ |
| D | marvel.rst | 29 Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible
69 Feroceon 88fr131 ARMv5 compatible
94 Feroceon 88fr571-vd ARMv5 compatible
241 ARMv5 compatible
293 - Core: ARMv5 XScale1 core
301 - Core: ARMv5 XScale2 core
312 - Core: ARMv5 XScale3 core
315 - Core: ARMv5 XScale3 core
349 - Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
354 - Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
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| /Linux-v5.10/arch/arm/include/asm/ |
| D | glue-df.h | 22 * v5t_early - ARMv5 with Thumb early abort handler
23 * v5tj_early - ARMv5 with Thumb and Java early abort handler
24 * xscale - ARMv5 with Thumb with Xscale extensions
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| D | cache.h | 21 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
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| D | processor.h | 107 * Prefetching support - only ARMv5.
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| D | bitops.h | 226 * On ARMv5 and above, the gcc built-ins may rely on the clz instruction
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| /Linux-v5.10/arch/arm/mach-sunxi/ |
| D | Kconfig | 68 bool "Allwinner ARMv5 F-series (suniv) SoCs support"
71 Support for Allwinner suniv ARMv5 SoCs.
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| /Linux-v5.10/arch/arm/mach-realview/ |
| D | Kconfig | 33 platform. On an ARMv5 kernel, this will include support for
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,integrator.yaml | 14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
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| /Linux-v5.10/arch/arm/mach-mmp/ |
| D | Kconfig | 109 bool "Support MMP (ARMv5) platforms from device tree"
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| /Linux-v5.10/arch/arm/probes/ |
| D | decode.h | 80 /* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
108 /* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
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| /Linux-v5.10/arch/arm/mm/ |
| D | fsr-2level.c | 4 * The following are the standard ARMv3 and ARMv4 aborts. ARMv5
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| D | cache-tauros2.c | 228 mode = "ARMv5"; in tauros2_internal_init()
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| D | proc-macros.S | 193 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
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| D | dump.c | 164 #else /* ARMv4/ARMv5 */
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| D | mmu.c | 444 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those in build_mem_type_table()
455 * ARMv5 and lower, bit 4 must be set for page tables (was: cache in build_mem_type_table()
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| /Linux-v5.10/arch/arm/kernel/ |
| D | tcm.c | 270 * Prior to ARMv5 there is no TCM, and trying to read the status in tcm_init()
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| D | perf_event_xscale.c | 3 * ARMv5 [xscale] Performance counter handling code.
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| /Linux-v5.10/drivers/irqchip/ |
| D | irq-mmp.c | 247 /* MMP (ARMv5) */
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| /Linux-v5.10/arch/arm/ |
| D | Kconfig | 562 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
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