Searched full:arcv2 (Results 1 – 25 of 32) sorted by relevance
12
| /Linux-v6.1/arch/arc/include/asm/ |
| D | arcregs.h | 10 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
18 #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
19 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
34 #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
37 #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
40 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
41 #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
45 /* Common for ARCompact and ARCv2 status register */
|
| D | fpu.h | 28 * ARCv2 FPU Control aux register
32 * ARCv2 FPU Status aux register
|
| D | irqflags.h | 13 #include <asm/irqflags-arcv2.h>
|
| D | mmu.h | 19 #include <asm/mmu-arcv2.h>
|
| D | irq.h | 10 * ARCv2 can support 240 interrupts in the core interrupts controllers and
|
| D | pgtable.h | 12 #include <asm/pgtable-bits-arcv2.h>
|
| D | atomic.h | 55 #include <asm/atomic64-arcv2.h>
|
| D | barrier.h | 12 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
|
| D | spinlock.h | 37 * ARCv2 only has load-load, store-store and all-all barrier in arch_spin_lock()
266 * RELEASE barrier: given the instructions avail on ARCv2, full barrier in arch_spin_unlock()
|
| D | entry-arcv2.h | 8 #include <asm/irqflags-arcv2.h>
12 * Interrupt/Exception stack layout (pt_regs) for ARCv2
|
| D | cache.h | 56 * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
|
| D | atomic64-arcv2.h | 4 * ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
|
| /Linux-v6.1/arch/arc/kernel/ |
| D | Makefile | 9 obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
|
| D | entry-arcv2.S | 3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
183 ;############# Common Handlers for ARCompact and ARCv2 ##############
187 ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
244 ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
|
| D | intc-arcv2.c | 59 * ARCv2 core intc provides multiple interrupt priorities (upto 16). in arc_init_IRQ()
126 .name = "ARCv2 core Intc",
|
| D | mcip.c | 13 #include <asm/irqflags-arcv2.h>
183 * ARCv2 Interrupt Distribution Unit (IDU)
300 * ARCv2 IDU HW does not support inverse polarity, so these are the in idu_irq_set_type()
|
| D | jump_label.c | 38 * ARCv2 'Branch unconditionally' instruction:
|
| D | process.c | 291 is_isa_arcompact() ? "ARCompact":"ARCv2"); in elf_check_arch()
|
| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,archs-intc.txt | 1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
|
| /Linux-v6.1/arch/arc/lib/ |
| D | memcpy-archs-unaligned.S | 3 * ARCv2 memcpy implementation optimized for unaligned memory access using.
|
| D | memcmp.S | 25 /* In ARCv2 a branch can't be the last instruction in a zero overhead
|
| /Linux-v6.1/Documentation/devicetree/bindings/remoteproc/ |
| D | amlogic,meson-mx-ao-arc.yaml | 13 ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA)
|
| /Linux-v6.1/drivers/clocksource/ |
| D | arc_timer.c | 11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
154 .name = "ARCv2 RTC",
|
| /Linux-v6.1/include/uapi/linux/ |
| D | elf-em.h | 50 #define EM_ARCV2 195 /* ARCv2 Cores */
|
| /Linux-v6.1/arch/arc/ |
| D | Kconfig | 131 Support for ARC HS38x Cores based on ARCv2 ISA
|
12
