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/Linux-v6.1/tools/testing/selftests/kvm/
D.gitignore2 /aarch64/aarch32_id_regs
3 /aarch64/arch_timer
4 /aarch64/debug-exceptions
5 /aarch64/get-reg-list
6 /aarch64/hypercalls
7 /aarch64/psci_test
8 /aarch64/vcpu_width_config
9 /aarch64/vgic_init
10 /aarch64/vgic_irq
DMakefile21 # for includes are in x86_64 sub-directory. s390x and aarch64 follow the
23 # s390x and aarch64.
30 UNAME_M := aarch64
61 LIBKVM_aarch64 += lib/aarch64/gic.c
62 LIBKVM_aarch64 += lib/aarch64/gic_v3.c
63 LIBKVM_aarch64 += lib/aarch64/handlers.S
64 LIBKVM_aarch64 += lib/aarch64/processor.c
65 LIBKVM_aarch64 += lib/aarch64/spinlock.c
66 LIBKVM_aarch64 += lib/aarch64/ucall.c
67 LIBKVM_aarch64 += lib/aarch64/vgic.c
[all …]
/Linux-v6.1/Documentation/arm64/
Dtagged-address-abi.rst2 AArch64 TAGGED ADDRESS ABI
11 ABI on AArch64 Linux.
16 On AArch64 the ``TCR_EL1.TBI0`` bit is set by default, allowing
22 2. AArch64 Tagged Address ABI
43 The AArch64 Tagged Address ABI has two stages of relaxation depending on
71 - ``PR_SET_TAGGED_ADDR_CTRL``: enable or disable the AArch64 Tagged
77 - ``PR_TAGGED_ADDR_ENABLE``: enable AArch64 Tagged Address ABI.
82 - ``PR_GET_TAGGED_ADDR_CTRL``: get the status of the AArch64 Tagged
91 returns ``-EINVAL`` if the AArch64 Tagged Address ABI is globally
95 When the AArch64 Tagged Address ABI is enabled for a thread, the
[all …]
Dtagged-pointers.rst2 Tagged virtual addresses in AArch64 Linux
10 addresses in the AArch64 translation system and their potential uses
11 in AArch64 Linux.
23 an address tag of 0x00, unless the application enables the AArch64
39 userspace application did not enable the AArch64 Tagged Address ABI may
43 For these reasons, when the AArch64 Tagged Address ABI is disabled,
79 This behaviour is maintained when the AArch64 Tagged Address ABI is
Dmemory.rst2 Memory Layout on AArch64 Linux
7 This document describes the virtual memory layout used by the AArch64
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
46 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
/Linux-v6.1/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c31 * Inject an unknown/undefined exception to an AArch64 guest while most of its
291 * Accessor for AArch64 feature id registers.
324 /* Mark the specified system register as an AArch64 feature id register. */
325 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 } macro
355 /* AArch64 mappings of the AArch32 ID registers */
386 /* AArch64 ID registers */
388 AARCH64(SYS_ID_AA64PFR0_EL1),
389 AARCH64(SYS_ID_AA64PFR1_EL1),
392 AARCH64(SYS_ID_AA64ZFR0_EL1),
396 AARCH64(SYS_ID_AA64DFR0_EL1),
[all …]
/Linux-v6.1/Documentation/translations/zh_TW/arm64/
Dmemory.txt31 Linux 在 AArch64 中的內存布局
36 本文檔描述 AArch64 Linux 內核所使用的虛擬內存布局。此構架可以實現
39 AArch64 Linux 使用 3 級或 4 級轉換表，其頁大小配置爲 4KB，對於用戶和內核
49 AArch64 Linux 在頁大小爲 4KB，並使用 3 級轉換表時的內存布局：
57 AArch64 Linux 在頁大小爲 4KB，並使用 4 級轉換表時的內存布局：
65 AArch64 Linux 在頁大小爲 64KB，並使用 2 級轉換表時的內存布局：
73 AArch64 Linux 在頁大小爲 64KB，並使用 3 級轉換表時的內存布局：
Dtagged-pointers.txt29 Linux 在 AArch64 中帶標記的虛擬地址
35 本文檔簡述了在 AArch64 地址轉換系統中提供的帶標記的虛擬地址及其在
36 AArch64 Linux 中的潛在用途。
Dbooting.txt31 啓動 AArch64 Linux
38 AArch64 Linux 內核代碼。
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
85 AArch64 內核當前沒有提供自解壓代碼，因此如果使用了壓縮內核映像文件
Damu.rst11 AArch64 Linux 中擴展的活動監控單元
18 本文檔簡要描述了 AArch64 Linux 支持的活動監控單元的規範。
/Linux-v6.1/Documentation/translations/zh_CN/arm64/
Dmemory.txt27 Linux 在 AArch64 中的内存布局
32 本文档描述 AArch64 Linux 内核所使用的虚拟内存布局。此构架可以实现
35 AArch64 Linux 使用 3 级或 4 级转换表，其页大小配置为 4KB，对于用户和内核
45 AArch64 Linux 在页大小为 4KB，并使用 3 级转换表时的内存布局：
53 AArch64 Linux 在页大小为 4KB，并使用 4 级转换表时的内存布局：
61 AArch64 Linux 在页大小为 64KB，并使用 2 级转换表时的内存布局：
69 AArch64 Linux 在页大小为 64KB，并使用 3 级转换表时的内存布局：
Dtagged-pointers.txt25 Linux 在 AArch64 中带标记的虚拟地址
31 本文档简述了在 AArch64 地址转换系统中提供的带标记的虚拟地址及其在
32 AArch64 Linux 中的潜在用途。
Dbooting.txt27 启动 AArch64 Linux
34 AArch64 Linux 内核代码。
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
81 AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内核映像文件
Damu.rst8 AArch64 Linux 中扩展的活动监控单元
15 本文档简要描述了 AArch64 Linux 支持的活动监控单元的规范。
/Linux-v6.1/arch/arm64/kvm/hyp/
Dexception.c72 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
75 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
78 * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from
124 // PSTATE.UAO is set to zero upon any exception to AArch64 in enter_exception64()
134 // PSTATE.SS is set to zero upon any exception to AArch64 in enter_exception64()
137 // PSTATE.IL is set to zero upon any exception to AArch64 in enter_exception64()
140 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 in enter_exception64()
145 // PSTATE.BTYPE is set to zero upon any exception to AArch64 in enter_exception64()
171 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
/Linux-v6.1/tools/testing/selftests/rcutorture/bin/
Dfunctions.sh159 qemu-system-aarch64)
184 elif echo $u | grep -q aarch64
186 echo qemu-system-aarch64
212 qemu-system-aarch64)
243 qemu-system-aarch64)
300 qemu-system-x86_64|qemu-system-i386|qemu-system-aarch64)
/Linux-v6.1/tools/perf/tests/shell/
Dtest_arm_spe.sh50 …# dd 3048 [002] 1 l1d-access: ffffaa64999c __GI___libc_write+0x3c (/lib/aarch64-…
51 …# dd 3048 [002] 1 tlb-access: ffffaa64999c __GI___libc_write+0x3c (/lib/aarch64-…
52 …# dd 3048 [002] 1 memory: ffffaa64999c __GI___libc_write+0x3c (/lib/aarch64-…
Dtest_arm_coresight.sh48 …# touch 6512 1 branches:u: ffffb220824c strcmp+0xc (/lib/aarch64-linux-gn…
49 …# touch 6512 1 branches:u: ffffb22082e0 strcmp+0xa0 (/lib/aarch64-linux-g…
50 …# touch 6512 1 branches:u: ffffb2208320 strcmp+0xe0 (/lib/aarch64-linux-g…
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dinstruction.json13 …unts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
20 …vent only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
/Linux-v6.1/tools/build/feature/
DMakefile46 test-libunwind-aarch64.bin \
48 test-libunwind-debug-frame-aarch64.bin \
191 $(OUTPUT)test-libunwind-aarch64.bin:
192 $(BUILD) -lelf -lunwind-aarch64
197 $(OUTPUT)test-libunwind-debug-frame-aarch64.bin:
198 $(BUILD) -lelf -lunwind-aarch64
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Darm,vexpress-juno.yaml16 32 bit (Aarch32) and 64 bit (Aarch64) systems.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
117 - description: Arm Foundation model for Aarch64
119 - const: arm,foundation-aarch64
/Linux-v6.1/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
47 use AArch64 naming convention.
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
/Linux-v6.1/tools/include/nolibc/
Darch-aarch64.h3 * AARCH64 specific definitions for NOLIBC
50 /* Syscalls for AARCH64 :
61 * On aarch64, select() is not implemented so we have to use pselect6().
/Linux-v6.1/drivers/firmware/efi/
Dcper-arm.c26 "AArch64 general purpose registers",
27 "AArch64 EL1 context registers",
28 "AArch64 EL2 context registers",
29 "AArch64 EL3 context registers",
/Linux-v6.1/arch/arm64/lib/
Dstrlen.S6 * https://github.com/ARM-software/optimized-routines/blob/98e4d6a5c13c8e54/string/aarch64/strlen.S
15 * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
75 AArch64 systems have a minimum page size of 4k. We don't bother

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