| /Linux-v5.15/Documentation/networking/ |
| D | 6pack.rst | 4 6pack Protocol
7 This is the 6pack-mini-HOWTO, written by
17 1. What is 6pack, and what are the advantages to KISS?
20 6pack is a transmission protocol for data exchange between the PC and
21 the TNC over a serial line. It can be used as an alternative to KISS.
23 6pack has two major advantages:
27 that the PC knows at any time if the TNC is receiving data, if a TNC
29 set and so on. This control data is processed at a higher priority than
30 normal data, so a data stream can be interrupted at any time to issue an
36 TNCs that are connected between each other and the PC by a daisy chain
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/ |
| D | mapfile.csv | 2 GenuineIntel-6-56,v5,broadwellde,core
3 GenuineIntel-6-3D,v17,broadwell,core
4 GenuineIntel-6-47,v17,broadwell,core
5 GenuineIntel-6-4F,v10,broadwellx,core
6 GenuineIntel-6-1C,v4,bonnell,core
7 GenuineIntel-6-26,v4,bonnell,core
8 GenuineIntel-6-27,v4,bonnell,core
9 GenuineIntel-6-36,v4,bonnell,core
10 GenuineIntel-6-35,v4,bonnell,core
11 GenuineIntel-6-5C,v8,goldmont,core
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| /Linux-v5.15/tools/testing/selftests/net/ |
| D | fcnal-test.sh | 13 # 6. VRF and non-VRF permutations
16 # ns-A | ns-B
23 # ns-A:
35 # ns-A to ns-C connection - only for VRF and same config
36 # as ns-A to ns-B
38 # server / client nomenclature relative to ns-A
77 NSA=ns-A
107 read a
108 [ "$a" = "q" ] && exit 1
115 read a
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| /Linux-v5.15/Documentation/dev-tools/ |
| D | kmemleak.rst | 4 Kmemleak provides a way of detecting possible kernel memory leaks in a
5 way similar to a `tracing garbage collector
8 reported via /sys/kernel/debug/kmemleak. A similar method is used by the
15 CONFIG_DEBUG_KMEMLEAK in "Kernel hacking" has to be enabled. A kernel
58 trigger a memory scan
86 information like size and stack trace, are stored in a rbtree.
94 block to a freeing function and therefore the block is considered a
103 a pointer to a white object is found, the object is added to the
115 block is not considered a leak. One example is __vmalloc().
124 /sys/kernel/debug/kmemleak output. By issuing a 'scan' after a 'clear'
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| /Linux-v5.15/Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
22 Some remotes have a pointer-type device which can used to control the
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
55 - 6 (inverted)
57 - 2nd start bit in rc5, re-used as 6th command bit
71 * - 6
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| /Linux-v5.15/Documentation/input/devices/ |
| D | elantech.rst | 24 5.2 Native absolute mode 6 byte packet format
28 6. Hardware version 3
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
57 combine a status packet with multiple head or motion packets. Hardware version
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
13 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
23 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins…
33 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
17 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
28 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
56 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | memory.json | 6 "CounterMask": "6",
16 "Counter": "0,1,2,3,4,5,6,7",
19 "PEBScounters": "0,1,2,3,4,5,6,7",
20 …ected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not …
27 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3,4,5,6,7",
66 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelake/ |
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
56 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
17 "Counter": "0,1,2,3,4,5,6,7",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
51 "PEBScounters": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
65 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
71 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
[all …]
|
| D | memory.json | 3 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
35 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
66 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
74 "Counter": "0,1,2,3,4,5,6,7",
77 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | pipeline.json | 9 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
14 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
20 …"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of sa…
30 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
41 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
47 …"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwar…
53 … prevented for a load operation. The most common case is a load blocked due to the address of memo…
77 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due …
85 "Counter": "0,1,2,3,4,5,6,7",
88 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| D | frontend.json | 105 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
111 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
141 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
147 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
155 "Counter": "0,1,2,3,4,5,6,7",
158 "PEBScounters": "0,1,2,3,4,5,6,7",
159 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
167 "Counter": "0,1,2,3,4,5,6,7",
171 "PEBScounters": "0,1,2,3,4,5,6,7",
172 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
[all …]
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| D | memory.json | 3 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
15 …"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitati…
21 … the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limita…
27 …"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitati…
33 … the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limita…
39 …tion": "Counts the number of times a class of instructions that may cause a transactional abort wa…
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
45 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
[all …]
|
| /Linux-v5.15/tools/thermal/tmon/ |
| D | tmon.8 | 4 \fBtmon\fP - A monitoring and testing tool for Linux kernel thermal subsystem
32 - with a built-in Proportional Integral Derivative (\fBPID\fP)
33 controller, user can pair a cooling device to a thermal sensor for
46 The \fB-c --control\fP option sets a cooling device type to control temperature
47 of a thermal zone
70 \fBA \fP active cooling trip point type (fan)
72 \fBA \fP hot trip point type
89 \fBTAB\fP shows tuning pop up panel, choose a letter to modify
115 LCD14 intel_powerclamp15 1 65.0 65 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2
116 65.0 66 65 0 0 0 0 0 0 0 0 0 0 4 4 4 4 6 0 3 65.0 60 54 0 0 0 0 0 0 0 0
[all …]
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| /Linux-v5.15/tools/testing/selftests/drivers/net/mlxsw/ |
| D | devlink_trap_control.sh | 96 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
101 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
112 ip -6 route add default vrf v$h2 nexthop via 2001:db8:2::2
117 ip -6 route del default vrf v$h2 nexthop via 2001:db8:2::2
220 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
221 -A 192.0.2.1 -B 224.0.0.1 -t ip proto=2,p=11 -p 100 -q
228 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
229 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=12 -p 100 -q
236 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
237 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=16 -p 100 -q
[all …]
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| /Linux-v5.15/arch/x86/crypto/ |
| D | sha256-avx-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
106 a = %eax define
140 # Rotate values of symbols a...h
149 b = a
150 a = TMP_ define
154 ## compute s0 four at a time and s1 two at a time
155 ## compute W[-16] + W[-7] 4 at a time
159 mov a, y1 # y1 = a
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| D | sha256-ssse3-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
99 a = %eax define
134 # Rotate values of symbols a...h
143 b = a
144 a = TMP_ define
148 ## compute s0 four at a time and s1 two at a time
149 ## compute W[-16] + W[-7] 4 at a time
153 mov a, y1 # y1 = a
155 ror $(22-13), y1 # y1 = a >> (22-13)
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
14 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
21 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
32 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
36 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
43 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
