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/Linux-v5.10/Documentation/networking/
D	6pack.rst	4 6pack Protocol 7 This is the 6pack-mini-HOWTO, written by 17 1. What is 6pack, and what are the advantages to KISS? 20 6pack is a transmission protocol for data exchange between the PC and 21 the TNC over a serial line. It can be used as an alternative to KISS. 23 6pack has two major advantages: 27 that the PC knows at any time if the TNC is receiving data, if a TNC 29 set and so on. This control data is processed at a higher priority than 30 normal data, so a data stream can be interrupted at any time to issue an 36 TNCs that are connected between each other and the PC by a daisy chain [all …]
/Linux-v5.10/tools/testing/selftests/net/
D	fcnal-test.sh	`13 # 6. VRF and non-VRF permutations 16 # ns-A \| ns-B 23 # ns-A: 35 # ns-A to ns-C connection - only for VRF and same config 36 # as ns-A to ns-B 38 # server / client nomenclature relative to ns-A 74 NSA=ns-A 104 read a 105 [ "$a" = "q" ] && exit 1 112 read a [all …]`
D	so_txtime.sh	`20 ./so_txtime -4 -6 -c mono a,-1 a,-1 21 ./so_txtime -4 -6 -c mono a,0 a,0 22 ./so_txtime -4 -6 -c mono a,10 a,10 23 ./so_txtime -4 -6 -c mono a,10,b,20 a,10,b,20 24 ./so_txtime -4 -6 -c mono a,20,b,10 b,20,a,20 27 ! ./so_txtime -4 -6 -c tai a,-1 a,-1 28 ! ./so_txtime -4 -6 -c tai a,0 a,0 29 ./so_txtime -4 -6 -c tai a,10 a,10 30 ./so_txtime -4 -6 -c tai a,10,b,20 a,10,b,20 31 ./so_txtime -4 -6 -c tai a,20,b,10 b,10,a,20`
/Linux-v5.10/Documentation/dev-tools/
D	kmemleak.rst	4 Kmemleak provides a way of detecting possible kernel memory leaks in a 5 way similar to a `tracing garbage collector 8 reported via /sys/kernel/debug/kmemleak. A similar method is used by the 15 CONFIG_DEBUG_KMEMLEAK in "Kernel hacking" has to be enabled. A kernel 58 trigger a memory scan 86 information like size and stack trace, are stored in a rbtree. 94 block to a freeing function and therefore the block is considered a 103 a pointer to a white object is found, the object is added to the 115 block is not considered a leak. One example is __vmalloc(). 124 /sys/kernel/debug/kmemleak output. By issuing a 'scan' after a 'clear' [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/
D	mapfile.csv	`2 GenuineIntel-6-56,v5,broadwellde,core 3 GenuineIntel-6-3D,v17,broadwell,core 4 GenuineIntel-6-47,v17,broadwell,core 5 GenuineIntel-6-4F,v10,broadwellx,core 6 GenuineIntel-6-1C,v4,bonnell,core 7 GenuineIntel-6-26,v4,bonnell,core 8 GenuineIntel-6-27,v4,bonnell,core 9 GenuineIntel-6-36,v4,bonnell,core 10 GenuineIntel-6-35,v4,bonnell,core 11 GenuineIntel-6-5C,v8,goldmont,core [all …]`
/Linux-v5.10/Documentation/userspace-api/media/rc/
D	rc-protos.rst	9 IR is encoded as a series of pulses and spaces, using a protocol. These 10 protocols can encode e.g. an address (which device should respond) and a 12 across different devices for a given protocol. 14 Therefore out the output of the IR decoder is a scancode; a single u32 17 Other things can be encoded too. Some IR protocols encode a toggle bit; this 22 Some remotes have a pointer-type device which can used to control the 32 This IR protocol uses manchester encoding to encode 14 bits. There is a 55 - 6 (inverted) 57 - 2nd start bit in rc5, re-used as 6th command bit 71 * - 6 [all …]
/Linux-v5.10/Documentation/userspace-api/media/v4l/
D	pixfmt-packed-yuv.rst	44 - 6 53 - 6 62 - 6 71 - 6 93 - a\ :sub:`3` 94 - a\ :sub:`2` 95 - a\ :sub:`1` 96 - a\ :sub:`0` 118 - a 158 - a\ :sub:`7` [all …]
D	pixfmt-rgb.rst	14 These are all packed-pixel formats, meaning all the data for a pixel lie 39 - 6 48 - 6 57 - 6 66 - 6 101 - a\ :sub:`3` 102 - a\ :sub:`2` 103 - a\ :sub:`1` 104 - a\ :sub:`0` 142 - a\ :sub:`3` [all …]
/Linux-v5.10/Documentation/input/devices/
D	elantech.rst	24 5.2 Native absolute mode 6 byte packet format 28 6. Hardware version 3 30 6.2 Native absolute mode 6 byte packet format 35 7.2 Native absolute mode 6 byte packet format 41 8.2 Native relative mode 6 byte packet format 52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes 54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and 55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking 56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can 57 combine a status packet with multiple head or motion packets. Hardware version [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/cascadelakex/
D	virtual-memory.json	3 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 8 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 13 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct… 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 18 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins… 23 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size… 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 28 …e sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The… 35 "CounterHTOff": "0,1,2,3,4,5,6,7", [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylakex/
D	virtual-memory.json	5 "CounterHTOff": "0,1,2,3,4,5,6,7", 14 "CounterHTOff": "0,1,2,3,4,5,6,7", 17 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M… 22 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", 24 "CounterHTOff": "0,1,2,3,4,5,6,7", 27 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 32 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct… 34 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins… 42 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylake/
D	virtual-memory.json	3 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/… 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 13 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 19 "BriefDescription": "Page walk completed due to a demand data load to a 4K page", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 23 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 29 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 33 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 39 "BriefDescription": "Page walk completed due to a demand data load to a 1G page", [all …]
D	pipeline.json	3 …a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable … 12 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event … 30 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i… 39 …a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible … 46 "CounterHTOff": "0,1,2,3,4,5,6,7" 56 "CounterHTOff": "0,1,2,3,4,5,6,7" 66 "CounterHTOff": "0,1,2,3,4,5,6,7" 76 "CounterHTOff": "0,1,2,3,4,5,6,7" 86 "CounterHTOff": "0,1,2,3,4,5,6,7" 95 "CounterHTOff": "0,1,2,3,4,5,6,7" [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/icelake/
D	pipeline.json	4 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event… 15 …"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of sa… 21 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP … 25 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event … 35 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i… 45 …a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible … 67 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M… 80 "Counter": "0,1,2,3,4,5,6,7", 82 "PEBScounters": "0,1,2,3,4,5,6,7", 89 …ription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buf… [all …]
D	frontend.json	110 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg… 117 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss." 143 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag … 150 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss." 154 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 156 "Counter": "0,1,2,3,4,5,6,7", 158 "PEBScounters": "0,1,2,3,4,5,6,7", 165 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 167 "Counter": "0,1,2,3,4,5,6,7", 169 "PEBScounters": "0,1,2,3,4,5,6,7", [all …]
D	memory.json	4 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 11 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on … 15 …nts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limita… 22 …"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation … 26 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/co… 33 …"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE pref… 37 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock … 48 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit b… 59 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an un… 81 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", [all …]
/Linux-v5.10/tools/thermal/tmon/
D	tmon.8	4 \fBtmon\fP - A monitoring and testing tool for Linux kernel thermal subsystem 32 - with a built-in Proportional Integral Derivative (\fBPID\fP) 33 controller, user can pair a cooling device to a thermal sensor for 46 The \fB-c --control\fP option sets a cooling device type to control temperature 47 of a thermal zone 70 \fBA \fP active cooling trip point type (fan) 72 \fBA \fP hot trip point type 89 \fBTAB\fP shows tuning pop up panel, choose a letter to modify 115 LCD14 intel_powerclamp15 1 65.0 65 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2 116 65.0 66 65 0 0 0 0 0 0 0 0 0 0 4 4 4 4 6 0 3 65.0 60 54 0 0 0 0 0 0 0 0 [all …]
/Linux-v5.10/tools/testing/selftests/drivers/net/mlxsw/
D	devlink_trap_control.sh	96 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2 101 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2 112 ip -6 route add default vrf v$h2 nexthop via 2001:db8:2::2 117 ip -6 route del default vrf v$h2 nexthop via 2001:db8:2::2 220 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \ 221 -A 192.0.2.1 -B 224.0.0.1 -t ip proto=2,p=11 -p 100 -q 228 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \ 229 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=12 -p 100 -q 236 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \ 237 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=16 -p 100 -q [all …]
D	fib_offload.sh	65 num=$(ip -6 route show match ${pfx} \| grep "offload" \| wc -l) 78 # Add a prefix route and check that it is offloaded. 79 ip -6 route add 2001:db8:3::/64 dev $spine_p1 metric 100 85 ip -6 route append 2001:db8:3::/64 dev $spine_p1 metric 200 93 ip -6 route append 2001:db8:3::/64 dev $spine_p1 metric 10 101 # Delete the routes and add the same route with a different nexthop 103 ip -6 route flush 2001:db8:3::/64 dev $spine_p1 104 ip -6 route add 2001:db8:3::/64 dev $spine_p2 109 ip -6 route flush 2001:db8:3::/64 116 # Add a multipath route and check that it is offloaded. [all …]
/Linux-v5.10/arch/x86/crypto/
D	sha256-avx-asm.S	`11 # This software is available to you under a choice of one of two 32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 47 # This code schedules 1 block at a time, with 4 lanes per block 106 a = %eax define 140 # Rotate values of symbols a...h 149 b = a 150 a = TMP_ define 154 ## compute s0 four at a time and s1 two at a time 155 ## compute W[-16] + W[-7] 4 at a time 159 mov a, y1 # y1 = a [all …]`
D	sha256-ssse3-asm.S	`11 # This software is available to you under a choice of one of two 32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 99 a = %eax define 134 # Rotate values of symbols a...h 143 b = a 144 a = TMP_ define 148 ## compute s0 four at a time and s1 two at a time 149 ## compute W[-16] + W[-7] 4 at a time 153 mov a, y1 # y1 = a 155 ror $(22-13), y1 # y1 = a >> (22-13) [all …]`
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwell/
D	virtual-memory.json	11 "CounterHTOff": "0,1,2,3,4,5,6,7" 14 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end … 21 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 22 "CounterHTOff": "0,1,2,3,4,5,6,7" 25 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can … 32 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 33 "CounterHTOff": "0,1,2,3,4,5,6,7" 36 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end … 43 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 44 "CounterHTOff": "0,1,2,3,4,5,6,7" [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellde/
D	virtual-memory.json	11 "CounterHTOff": "0,1,2,3,4,5,6,7" 16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end … 22 "CounterHTOff": "0,1,2,3,4,5,6,7" 27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can … 33 "CounterHTOff": "0,1,2,3,4,5,6,7" 38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end … 44 "CounterHTOff": "0,1,2,3,4,5,6,7" [all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/
D	virtual-memory.json	11 "CounterHTOff": "0,1,2,3,4,5,6,7" 16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end … 22 "CounterHTOff": "0,1,2,3,4,5,6,7" 27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl… 31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can … 33 "CounterHTOff": "0,1,2,3,4,5,6,7" 38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end … 44 "CounterHTOff": "0,1,2,3,4,5,6,7" [all …]
/Linux-v5.10/arch/microblaze/include/asm/
D	hash.h	8 * a supported configuration. 10 * With just a barrel shifter, we can implement an efficient constant 11 * multiply using shifts and adds. GCC can find a 9-step solution, but 12 * this 6-step solution was found by Yevgen Voronenko's implementation 15 * That software is really not designed for a single multiplier this large, 17 * 6-shift, 6-add sequences for computing x * 0x61C88647. They are all 19 * a = (x << 9) + c; 20 * b = (x << 23) + a; 21 * return (a<<11) + (b<<6) + (c<<3) - b; 24 * Without even a shifter, it's hopless; any hash function will suck. [all …]

12 3 4 5 6 7 8 9 10 >>...60