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/Linux-v6.6/arch/x86/kernel/
Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/Linux-v6.6/arch/arm/mach-omap2/
Dopp2xxx.h70 #define R1_CLKSEL_L4 (2 << 5)
78 #define R1_CLKSEL_DSP_IF (2 << 5)
87 #define R2_CLKSEL_L4 (2 << 5)
95 #define R2_CLKSEL_DSP_IF (3 << 5)
104 #define RB_CLKSEL_L4 (1 << 5)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
[all …]
Dopp2430_data.c22 * XXX Missing 19.2MHz sys_clk rate sets.
56 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
64 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
71 /* PRCM #5a - ratio1 - FAST */
72 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
79 /* PRCM #5b - ratio1 - FAST */
80 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
88 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
96 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
103 /* PRCM #5a - ratio1 - SLOW */
[all …]
/Linux-v6.6/Documentation/userspace-api/media/dvb/
Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
44 - .. row 5
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
[all …]
/Linux-v6.6/drivers/net/wireless/ti/wl12xx/
Dwl12xx.h27 #define WL127X_IFTYPE_MR_VER 5
40 #define WL128X_IFTYPE_MR_VER 5
73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
[all …]
/Linux-v6.6/drivers/clk/mvebu/
Ddove.c25 * SAR0[8:5] : CPU frequency
26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
[all …]
Dkirkwood.c28 * 4 = 600 MHz
29 * 6 = 800 MHz
30 * 7 = 1000 MHz
31 * 9 = 1200 MHz
32 * 12 = 1500 MHz
33 * 13 = 1600 MHz
34 * 14 = 1800 MHz
35 * 15 = 2000 MHz
41 * 5 = (1/4) * CPU
44 * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
[all …]
Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
161 { "pex00", NULL, 5, 0 },
/Linux-v6.6/drivers/media/usb/dvb-usb-v2/
Daf9035.h81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
88 34000000, /* 34.00 MHz */
89 24000000, /* 24.00 MHz */
90 22000000, /* 22.00 MHz */
[all …]
/Linux-v6.6/drivers/net/ethernet/intel/ice/
Dice_ptp_consts.h23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
/Linux-v6.6/drivers/clk/spear/
Dspear1310_clock.c128 #define SPEAR1310_SMI_CLK_ENB 5
140 #define SPEAR1310_GPT3_CLK_ENB 5
161 #define SPEAR1310_C48M_CLK_ENB 5
220 #define SPEAR1310_PCI_CLK_ENB 5
231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
[all …]
Dspear1340_clock.c124 #define SPEAR1340_SMI_CLK_ENB 5
135 #define SPEAR1340_GPT3_CLK_ENB 5
154 #define SPEAR1340_CEC0_CLK_ENB 5
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
109 #define NUM_VCN_DPM_LEVELS 5
124 //Freq in MHz
160 #define THROTTLER_STATUS_BIT_THM_GFX 5
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
171 uint16_t DclkFrequency; //[MHz]
[all …]
Dsmu13_driver_if_yellow_carp.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
119 //Freq in MHz
149 #define THROTTLER_STATUS_BIT_THM_GFX 5
159 uint16_t GfxclkFrequency; //[MHz]
160 uint16_t SocclkFrequency; //[MHz]
161 uint16_t VclkFrequency; //[MHz]
162 uint16_t DclkFrequency; //[MHz]
163 uint16_t MemclkFrequency; //[MHz]
[all …]
Dsmu13_driver_if_v13_0_4.h46 uint16_t Freq; // in MHz
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
120 //Freq in MHz
150 #define THROTTLER_STATUS_BIT_THM_GFX 5
160 uint16_t GfxclkFrequency; //[MHz]
161 uint16_t SocclkFrequency; //[MHz]
162 uint16_t VclkFrequency; //[MHz]
163 uint16_t DclkFrequency; //[MHz]
164 uint16_t MemclkFrequency; //[MHz]
[all …]
Dsmu12_driver_if.h46 uint16_t Freq; // in MHz
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
112 uint32_t Freq; // In MHz
162 #define THROTTLER_STATUS_BIT_THM_GFX 5
172 uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
174 uint16_t AverageGfxclkFrequency; //[MHz]
175 uint16_t AverageSocclkFrequency; //[MHz]
176 uint16_t AverageVclkFrequency; //[MHz]
177 uint16_t AverageFclkFrequency; //[MHz]
[all …]
/Linux-v6.6/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi42 atlas0_alert_5: atlas0-alert-5 {
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
76 cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
77 <&cpu6 4 5>, <&cpu7 4 5>;
80 /* Set maximum frequency as 1400MHz */
82 cooling-device = <&cpu4 5 7>, <&cpu5 5 7>,
83 <&cpu6 5 7>, <&cpu7 5 7>;
[all …]
/Linux-v6.6/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
85 # 5 chars 1 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/Linux-v6.6/drivers/clk/samsung/
Dclk-exynos3250.c96 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
235 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
457 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
496 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
605 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
625 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
633 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
650 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
675 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
Dclk-exynos4.c131 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
450 CLKOUT_CMU_LEFTBUS, 0, 5),
454 CLKOUT_CMU_RIGHTBUS, 0, 5),
501 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
504 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
506 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
514 CLKOUT_CMU_LEFTBUS, 0, 5),
519 CLKOUT_CMU_RIGHTBUS, 0, 5),
523 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
582 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
[all …]
/Linux-v6.6/drivers/media/dvb-frontends/
Dhelene.c54 /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
56 /**< System-M (US) (IF: Fp=5.75MHz in default) */
58 /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
60 /**< System-B/G (IF: Fp=7.3MHz in default) */
62 /**< System-I (IF: Fp=7.85MHz in default) */
64 /**< System-D/K (IF: Fp=7.85MHz in default) */
66 /**< System-L (IF: Fp=7.85MHz in default) */
68 /**< System-L DASH (IF: Fp=2.2MHz in default) */
71 /**< ATSC 8VSB (IF: Fc=3.7MHz in default) */
73 /**< US QAM (IF: Fc=3.7MHz in default) */
[all …]
/Linux-v6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/Linux-v6.6/drivers/clk/uniphier/
Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
[all …]
/Linux-v6.6/tools/testing/selftests/intel_pstate/
Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
58 echo "sleeping for 5 seconds"
59 sleep 5
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
[all …]
/Linux-v6.6/Documentation/admin-guide/pm/
Dintel-speed-select.rst152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
181 enable-cpu-list:0,1,2,3,5,7,8,9,10,11,28,29,30,31,33,35,36,37,38,39
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
[all …]

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