| /Linux-v5.15/tools/testing/selftests/vm/ |
| D | mremap_dontunmap.c | 43 // Try a simple operation for to "test" for kernel support this prevents
100 unsigned long num_pages = 5; in mremap_dontunmap_simple()
107 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
116 // the dest_mapping contains a's. in mremap_dontunmap_simple()
118 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
130 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
133 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
148 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
164 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
166 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
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| /Linux-v5.15/arch/alpha/lib/ |
| D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
13 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
23 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins…
33 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
17 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
28 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
56 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | memory.json | 16 "Counter": "0,1,2,3,4,5,6,7",
19 "PEBScounters": "0,1,2,3,4,5,6,7",
20 …ected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not …
27 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3,4,5,6,7",
66 "PEBScounters": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
17 "Counter": "0,1,2,3,4,5,6,7",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
33 "CounterMask": "5",
45 "Counter": "0,1,2,3,4,5,6,7",
51 "PEBScounters": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7",
61 "CounterMask": "5",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
33 …s during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | memory.json | 3 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
35 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
66 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
74 "Counter": "0,1,2,3,4,5,6,7",
77 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 18 "CounterMask": "5",
56 "CounterMask": "5",
105 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
111 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
141 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
147 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
155 "Counter": "0,1,2,3,4,5,6,7",
158 "PEBScounters": "0,1,2,3,4,5,6,7",
159 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
167 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| D | pipeline.json | 9 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
14 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
20 …"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of sa…
30 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
41 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
47 …"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwar…
53 … prevented for a load operation. The most common case is a load blocked due to the address of memo…
77 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due …
85 "Counter": "0,1,2,3,4,5,6,7",
88 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | memory.json | 3 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
15 …"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitati…
21 … the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limita…
27 …"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitati…
33 … the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limita…
39 …tion": "Counts the number of times a class of instructions that may cause a transactional abort wa…
41 "Counter": "0,1,2,3,4,5,6,7",
44 "PEBScounters": "0,1,2,3,4,5,6,7",
45 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
[all …]
|
| /Linux-v5.15/Documentation/input/devices/ |
| D | elantech.rst | 22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
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| D | alps.rst | 8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
11 integrated into a variety of laptops and netbooks. These new touchpads
23 (Compatibility ID) definition as a way to uniquely identify the
24 different ALPS variants but there did not appear to be a 1:1 mapping.
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
51 Protocol versions 3 and 4 have a command mode that is used to read and write
52 one-byte device registers in a 16-bit address space. The command sequence
54 with 88-07 followed by a third byte. This third byte can be used to determine
59 While in command mode, register addresses can be set by first sending a
[all …]
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| /Linux-v5.15/arch/s390/lib/ |
| D | uaccess.c | 79 " jnh 5f\n" in copy_from_user_mvcos()
82 " j 5f\n" in copy_from_user_mvcos()
84 "5:\n" in copy_from_user_mvcos()
85 EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b) in copy_from_user_mvcos()
86 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcos()
101 "7: jz 5f\n" in copy_from_user_mvcp()
107 " j 5f\n" in copy_from_user_mvcp()
117 "5: slgr %0,%0\n" in copy_from_user_mvcp()
121 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcp()
152 " jnh 5f\n" in copy_to_user_mvcos()
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
14 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
21 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
32 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
36 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
43 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| D | cache.json | 10 "CounterHTOff": "0,1,2,3,4,5,6,7"
19 "CounterHTOff": "0,1,2,3,4,5,6,7"
28 "CounterHTOff": "0,1,2,3,4,5,6,7"
37 "CounterHTOff": "0,1,2,3,4,5,6,7"
47 "CounterHTOff": "0,1,2,3,4,5,6,7"
56 "CounterHTOff": "0,1,2,3,4,5,6,7"
66 "CounterHTOff": "0,1,2,3,4,5,6,7"
75 "CounterHTOff": "0,1,2,3,4,5,6,7"
84 "CounterHTOff": "0,1,2,3,4,5,6,7"
94 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| D | memory.json | 10 "CounterHTOff": "0,1,2,3,4,5,6,7"
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 "BriefDescription": "Number of times a TSX line had a cache conflict",
28 "PublicDescription": "Number of times a TSX line had a cache conflict.",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
35 …"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a …
38 …"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a…
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
45 …"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store t…
48 …"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store …
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /Linux-v5.15/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
38 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
53 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
54 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 (a) L3C PMU supports filtering by core/thread within the cluster which can be
60 specified as a bitmap::
62 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
72 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
76 (c) Datasrc allows the user to check where the data comes from. It is 5 bits.
78 5'b00001: comes from L3C in this die;
[all …]
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| /Linux-v5.15/arch/powerpc/crypto/ |
| D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
46 .long R(5f, a2, a2, fd), R(45, af, af, ea)
48 .long R(e4, 72, 72, 96), R(9b, c0, c0, 5b)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
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| /Linux-v5.15/arch/m68k/fpsp040/ |
| D | tbldo.S | 10 | index with a 10-bit index, with the first
54 .long smovcr |$00-5 fmovecr all
63 .long serror |$01-5 fint ERROR
72 .long serror |$02-5 fsinh ERROR
81 .long serror |$03-5 fintrz ERROR
90 .long serror |$04-5 ERROR - illegal extension
99 .long serror |$05-5 ERROR - illegal extension
108 .long serror |$06-5 flognp1 ERROR
117 .long serror |$07-5 ERROR - illegal extension
126 .long serror |$08-5 fetoxm1 ERROR
[all …]
|
