| /Linux-v6.1/drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
30 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
34 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
38 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
62 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
107 /* Relative to priv->regmap */
128 * A lane is described by the following bitfields:
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| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
39 * When accessing common PHY lane registers directly, we need to shift by 1,
40 * since the registers are 16-bit.
54 #define REF_FREF_SEL_MASK GENMASK(4, 0)
76 #define PLL_READY_TX_BIT BIT(4)
109 #define CLK100M_125M_EN BIT(4)
129 #define PRD_TXSWING_MASK BIT(4)
136 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
151 #define MODE_REFDIV_MASK GENMASK(5, 4)
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| D | phy-armada38x-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
51 { 4, 5, 0 },
52 { 0, 4, 0 },
53 { 0, 0, 4 },
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
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| /Linux-v6.1/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
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| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
96 #define HSIC_PD_RX_DATA0 BIT(4)
118 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
121 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
126 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
129 #define HSIC_CAP_CFG BIT(4)
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| /Linux-v6.1/sound/soc/tegra/ |
| D | tegra186_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
32 (((id) + 1) << 4) }, \
49 ASRC_STREAM_REG_DEFAULTS(4),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
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| /Linux-v6.1/drivers/phy/ |
| D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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| /Linux-v6.1/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
94 #define L3_NSW_PIPE_SHIFT 4
104 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
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| /Linux-v6.1/include/linux/phy/ |
| D | phy-mipi-dphy.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
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| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
33 * Allowed values: 1, 2, 4
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
46 unsigned int voltage[4];
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
56 unsigned int pre[4];
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| /Linux-v6.1/drivers/media/platform/ti/omap3isp/ |
| D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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| /Linux-v6.1/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
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| /Linux-v6.1/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
96 writel(value, padctl->regs + offset); in padctl_writel()
102 return readl(padctl->regs + offset); in padctl_readl()
109 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
117 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
126 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
127 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
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| /Linux-v6.1/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
44 /* 10GBASE-R and 10GBASE-X4/X2 */
51 /* 1000BASE-X and SGMII */
113 int lane, unsigned int mode,
117 int lane, unsigned int mode,
121 int lane, struct phylink_link_state *state);
123 int lane, struct phylink_link_state *state);
125 int lane, struct phylink_link_state *state);
127 int lane, struct phylink_link_state *state);
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| D | serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
56 state->link = false; in mv88e6xxx_serdes_pcs_get_state()
64 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state()
65 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_serdes_pcs_get_state()
72 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state()
77 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_serdes_pcs_get_state()
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| /Linux-v6.1/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 50 link->ctx->logger
133 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval()
160 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
173 case 4: return 16000; in get_eq_training_aux_rd_interval()
276 struct dpcd_caps *rx_caps = &link->dpcd_caps; in decide_eq_training_pattern()
281 enc_caps = &link_enc->features; in decide_eq_training_pattern()
285 if (enc_caps->flags.bits.IS_TPS4_CAPABLE && in decide_eq_training_pattern()
286 rx_caps->max_down_spread.bits.TPS4_SUPPORTED) in decide_eq_training_pattern()
288 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE && in decide_eq_training_pattern()
289 rx_caps->max_ln_count.bits.TPS3_SUPPORTED) in decide_eq_training_pattern()
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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| /Linux-v6.1/drivers/phy/amlogic/ |
| D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
25 * [30] clock lane soft reset.
26 * [29] data byte lane 3 soft reset.
27 * [28] data byte lane 2 soft reset.
28 * [27] data byte lane 1 soft reset.
29 * [26] data byte lane 0 soft reset.
37 * 1: /4. 0: /2.
43 * [4] HS data endian.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
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| /Linux-v6.1/drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
13 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
126 #define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
201 #define TXDA_UPHY_SUPPLY_EN_DEL BIT(4)
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| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation
31 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
36 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
43 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
50 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_read_lttpr_phy_caps()
53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
54 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
56 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
61 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
63 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
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| /Linux-v6.1/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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| /Linux-v6.1/sound/soc/meson/ |
| D | axg-tdmout.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <sound/soc-dai.h>
12 #include "axg-tdm-formatter.h"
15 #define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)
25 #define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
26 #define TDMOUT_CTRL1_TYPE(x) ((x) << 4)
51 .reg_stride = 4,
62 if (!p->connect) in axg_tdmout_get_be()
65 if (p->sink->id == snd_soc_dapm_dai_in) in axg_tdmout_get_be()
66 return (struct snd_soc_dai *)p->sink->priv; in axg_tdmout_get_be()
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| /Linux-v6.1/drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
44 /* Per SerDes lane registers */
45 /* Lane a General Control Register */
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
54 /* Lane a Tx Reset Control Register */
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
60 /* Lane a Tx General Control Register */
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
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