| /Linux-v5.10/drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
30 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
34 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
38 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
62 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
107 /* Relative to priv->regmap */
128 * A lane is described by the following bitfields:
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| D | phy-armada38x-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
51 { 4, 5, 0 },
52 { 0, 4, 0 },
53 { 0, 0, 4 },
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
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| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
45 #define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
58 unsigned int lane; member
67 .lane = _lane, \
81 /* lane 0 */
88 /* lane 1 */
95 /* lane 2 */
110 static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, in mvebu_a3700_comphy_smc() argument
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| /Linux-v5.10/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
158 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
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| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
96 #define HSIC_PD_RX_DATA0 BIT(4)
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
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| /Linux-v5.10/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
94 #define L3_NSW_PIPE_SHIFT 4
104 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
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| /Linux-v5.10/drivers/phy/ |
| D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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| /Linux-v5.10/include/linux/phy/ |
| D | phy-mipi-dphy.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
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| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
33 * Allowed values: 1, 2, 4
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
46 unsigned int voltage[4];
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
56 unsigned int pre[4];
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| /Linux-v5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation
34 link_status[3], link_status[4], link_status[5]); in intel_dp_dump_link_status()
58 int lane; in intel_dp_get_adjust_train() local
62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train()
64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train()
67 preemph_max = intel_dp->preemph_max(intel_dp); in intel_dp_get_adjust_train()
68 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
77 voltage_max = intel_dp->voltage_max(intel_dp); in intel_dp_get_adjust_train()
78 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
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| /Linux-v5.10/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
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| /Linux-v5.10/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
42 /* 10GBASE-R and 10GBASE-X4/X2 */
46 /* 1000BASE-X and SGMII */
81 u8 lane, unsigned int mode,
85 u8 lane, unsigned int mode,
89 u8 lane, struct phylink_link_state *state);
91 u8 lane, struct phylink_link_state *state);
93 u8 lane);
95 u8 lane);
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 19 link->ctx->logger
38 /* to avoid infinite loop where-in the receiver
78 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
79 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval()
133 struct encoder_feature_support *features = &link->link_enc->features; in decide_eq_training_pattern()
134 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern()
136 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern()
139 if (features->flags.bits.IS_TPS4_CAPABLE) in decide_eq_training_pattern()
142 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in decide_eq_training_pattern()
146 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && in decide_eq_training_pattern()
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| /Linux-v5.10/drivers/media/platform/omap3isp/ |
| D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
121 "ScaleUnit": "7.11E-06Bytes",
133 "ScaleUnit": "4Bytes",
145 "ScaleUnit": "4Bytes",
157 "ScaleUnit": "4Bytes",
169 "ScaleUnit": "4Bytes",
184 "ScaleUnit": "4Bytes",
196 "ScaleUnit": "4Bytes",
208 "ScaleUnit": "4Bytes",
220 "ScaleUnit": "4Bytes",
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
121 "ScaleUnit": "7.11E-06Bytes",
133 "ScaleUnit": "4Bytes",
145 "ScaleUnit": "4Bytes",
157 "ScaleUnit": "4Bytes",
169 "ScaleUnit": "4Bytes",
184 "ScaleUnit": "4Bytes",
196 "ScaleUnit": "4Bytes",
208 "ScaleUnit": "4Bytes",
220 "ScaleUnit": "4Bytes",
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| /Linux-v5.10/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
44 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
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| /Linux-v5.10/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
96 writel(value, padctl->regs + offset); in padctl_writel()
102 return readl(padctl->regs + offset); in padctl_readl()
109 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
117 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
126 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
127 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
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| /Linux-v5.10/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
82 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
84 if (!dp->force_hpd) in analogix_dp_detect_hpd()
85 return -ETIMEDOUT; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
97 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
98 return -EINVAL; in analogix_dp_detect_hpd()
101 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
111 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
113 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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| /Linux-v5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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| /Linux-v5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
13 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
126 #define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
201 #define TXDA_UPHY_SUPPLY_EN_DEL BIT(4)
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| D | phy-rockchip-inno-dsidphy.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
30 * when you configure the registers, you must set both of them. The Clock Lane
31 * and Data Lane use the same registers with the same second address, but the
46 #define LANE_EN_2 BIT(4)
65 #define REG_PREDIV_MASK GENMASK(4, 0)
66 #define REG_PREDIV(x) UPDATE(x, 4, 0)
71 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
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| /Linux-v5.10/include/linux/platform_data/media/ |
| D | omap4iss.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
24 #define ISS_CSIPHY1_NUM_DATA_LANES 4
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
30 * @clk: Clock lane configuration
38 * struct iss_csi2_platform_data - CSI2 interface platform data
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| /Linux-v5.10/sound/soc/meson/ |
| D | axg-tdmout.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <sound/soc-dai.h>
12 #include "axg-tdm-formatter.h"
15 #define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)
25 #define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
26 #define TDMOUT_CTRL1_TYPE(x) ((x) << 4)
51 .reg_stride = 4,
62 if (!p->connect) in axg_tdmout_get_be()
65 if (p->sink->id == snd_soc_dapm_dai_in) in axg_tdmout_get_be()
66 return (struct snd_soc_dai *)p->sink->priv; in axg_tdmout_get_be()
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