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/Linux-v6.6/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
31 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
35 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
39 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
63 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
108 /* Relative to priv->regmap */
129 * A lane is described by the following bitfields:
[all …]
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
77 #define PLL_READY_TX_BIT BIT(4)
110 #define CLK100M_125M_EN BIT(4)
130 #define PRD_TXSWING_MASK BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
[all …]
Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 { 4, 5, 0 },
53 { 0, 4, 0 },
54 { 0, 0, 4 },
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
61 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
64 if (priv->conf) { in a38x_set_conf()
65 conf = readl_relaxed(priv->conf); in a38x_set_conf()
67 conf |= BIT(lane->port); in a38x_set_conf()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
[all …]
/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
74 #define XELPDP_TCSS_POWER_STATE REG_BIT(4)
82 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
[all …]
Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
55 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
66 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
75 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
83 enum port port, int lane) in intel_clear_response_ready_flag() argument
85 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), in intel_clear_response_ready_flag()
89 static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane) in intel_cx0_bus_reset() argument
93 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), in intel_cx0_bus_reset()
96 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), in intel_cx0_bus_reset()
99 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
[all …]
Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
30 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \
31 (_intel_dp)->attached_connector->base.name, \
32 dp_to_dig_port(_intel_dp)->base.base.base.id, \
33 dp_to_dig_port(_intel_dp)->base.base.name, \
37 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \
42 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
43 drm_err(&dp_to_i915(_intel_dp)->drm, \
52 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
57 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
[all …]
/Linux-v6.6/drivers/phy/tegra/
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
[all …]
Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
[all …]
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
101 #define HSIC_PD_RX_DATA0 BIT(4)
123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
134 #define HSIC_CAP_CFG BIT(4)
[all …]
/Linux-v6.6/sound/soc/tegra/
Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
32 (((id) + 1) << 4) }, \
49 ASRC_STREAM_REG_DEFAULTS(4),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
[all …]
/Linux-v6.6/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
94 #define L3_NSW_PIPE_SHIFT 4
104 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
[all …]
/Linux-v6.6/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/Linux-v6.6/include/linux/phy/
Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
[all …]
Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
33 * Allowed values: 1, 2, 4
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
46 unsigned int voltage[4];
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
56 unsigned int pre[4];
[all …]
/Linux-v6.6/drivers/media/platform/ti/omap3isp/
Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
/Linux-v6.6/drivers/platform/x86/intel/pmc/
Dspt.c1 // SPDX-License-Identifier: GPL-2.0
22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
[all …]
/Linux-v6.6/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
[all …]
/Linux-v6.6/drivers/pinctrl/tegra/
Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
129 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
130 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
[all …]
/Linux-v6.6/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/
Duncore-io.json148 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
154 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
165 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
187 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
198 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
203 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
209 … : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is …
220 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
231 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
/Linux-v6.6/drivers/phy/amlogic/
Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
25 * [30] clock lane soft reset.
26 * [29] data byte lane 3 soft reset.
27 * [28] data byte lane 2 soft reset.
28 * [27] data byte lane 1 soft reset.
29 * [26] data byte lane 0 soft reset.
37 * 1: /4. 0: /2.
43 * [4] HS data endian.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/cascadelakex/
Duncore-io.json12 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
13 "ScaleUnit": "4Bytes",
27 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
28 "ScaleUnit": "4Bytes",
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
131 "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
182 …ouble word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged …
193 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
204 …on": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; …
215 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
[all …]
/Linux-v6.6/tools/perf/pmu-events/arch/x86/skylakex/
Duncore-io.json12 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
13 "ScaleUnit": "4Bytes",
27 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
28 "ScaleUnit": "4Bytes",
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
131 "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
182 …ouble word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged …
193 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
204 …on": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; …
215 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
[all …]

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