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/Linux-v6.1/arch/arm64/crypto/
Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
14 .arch armv8-a+crypto
16 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 16, 20, 24, 25, 26, 27, 28, 29, 30, 31
17 .set .Lv\b\().4s, \b
25 .inst 0xce60c800 | (.L\vm << 16) | (.L\vn << 5) | .L\vd
40 ld1 {v24.16b-v27.16b}, [x0], #64; \
41 ld1 {v28.16b-v31.16b}, [x0];
44 rev32 b0.16b, b0.16b; \
45 sm4e b0.4s, v24.4s; \
[all …]
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
42 ld1 {v12.4s}, [x10]
45 // x0 += x1, x3 = rotl32(x3 ^ x0, 16)
46 add v0.4s, v0.4s, v1.4s
47 eor v3.16b, v3.16b, v0.16b
51 add v2.4s, v2.4s, v3.4s
[all …]
Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
30 ld1 {v16.16b-v19.16b}, [x5], #64; \
31 ld1 {v20.16b-v23.16b}, [x5], #64; \
32 ld1 {v24.16b-v27.16b}, [x5], #64; \
33 ld1 {v28.16b-v31.16b}, [x5];
36 zip1 RTMP0.4s, s0.4s, s1.4s; \
37 zip1 RTMP1.4s, s2.4s, s3.4s; \
38 zip2 RTMP2.4s, s0.4s, s1.4s; \
39 zip2 RTMP3.4s, s2.4s, s3.4s; \
[all …]
Dsm3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
13 .set .Lv\b\().4s, \b
17 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
21 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
33 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
37 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
40 .align 4
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
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Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
14 ld1 {v1.4s}, [x0], #16
18 mov v3.16b, v1.16b
20 0: mov v2.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
[all …]
Dsha2-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
30 mov dg2v.16b, dg0v.16b
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
[all …]
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
21 sub w3, w3, #16
22 eor v1.16b, v1.16b, v1.16b
27 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
30 eor v0.16b, v0.16b, v1.16b
31 1: ld1 {v3.4s}, [x4] /* load first round key */
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/Linux-v6.1/tools/testing/selftests/powerpc/lib/
Dreg.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 #include <ppc-asm.h>
11 /* Non volatile GPR - unsigned long buf[18] */
15 ld 16, 2*8(3)
17 ld 18, 4*8(3)
29 ld 30, 16*8(3)
37 std 16, 2*8(3)
39 std 18, 4*8(3)
51 std 30, 16*8(3)
56 /* Double Precision Float - double buf[32] */
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/Linux-v6.1/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
23 - e GRBG 0
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/Linux-v6.1/arch/x86/crypto/
Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
23 #define kr (16*4)
24 #define rr ((16*4)+16)
26 /* s-boxes */
33 16-way AVX cast5
88 shrq $16, src; \
89 movl s1(, RID1, 4), dst ## d; \
[all …]
/Linux-v6.1/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
55 bis $16,$16,$0 # E : return value
[all …]
Dcopy_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Notably, we have to make sure that $0 is always up-to-date and
21 .long 99b - .; \
22 lda $31, $exitin-99b($31); \
28 .long 99b - .; \
29 lda $31, $exitout-99b($31); \
33 .align 4
39 and $16,7,$3
43 .align 4
46 EXO( ldq_u $2,0($16) )
[all …]
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
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Dclear_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
25 .align 4
33 and $1, 3, $4 # e0 :
34 beq $4, 1f # .. e1 :
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
38 subq $4, 1, $4 # e0 :
39 addq $16, 8, $16 # .. e1 :
[all …]
/Linux-v6.1/drivers/gpu/drm/vmwgfx/device_include/
Dsvga3d_surfacedefs.h2 * Copyright 2008-2021 VMware, Inc.
3 * SPDX-License-Identifier: GPL-2.0 OR MIT
28 * svga3d_surfacedefs.h --
71 SVGA3DBLOCKDESC_BUFFER = 1 << 4,
93 SVGA3DBLOCKDESC_SRGB = 1 << 16,
335 4,
336 4,
338 { { 0 }, { 8 }, { 16 }, { 24 } } },
343 4,
344 4,
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/Linux-v6.1/include/soc/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
40 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
44 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
48 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
51 #define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
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/Linux-v6.1/drivers/net/ethernet/cavium/thunder/
Dq_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
124 CQE_RX_TCP_END_PKT_ERR = 4,
173 u64 cqe_type:4; /* W0 */
179 u64 rss_alg:4;
180 u64 rsvd2:4;
181 u64 rb_cnt:4;
186 u64 l4_type:4;
187 u64 l3_type:4;
192 u64 pkt_len:16; /* W1 */
202 u64 vlan_tci:16;
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/Linux-v6.1/tools/testing/selftests/powerpc/copyloops/
Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
56 /* first check for a 4kB copy on a 4kB boundary */
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/Linux-v6.1/arch/powerpc/lib/
Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
56 /* first check for a 4kB copy on a 4kB boundary */
[all …]
/Linux-v6.1/include/dt-bindings/memory/
Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
14 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
26 * N/A 12G ~ 16G
28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
[all …]
/Linux-v6.1/arch/microblaze/lib/
Dfastcopy.S2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2008-2009 PetaLogix
4 * Copyright (C) 2008 Jim Law - Iris LP All rights reserved.
21 * Input : Operand1 in Reg r5 - destination address
22 * Operand2 in Reg r6 - source address
23 * Operand3 in Reg r7 - number of bytes to transfer
24 * Output: Result in Reg r3 - starting destinaition address
43 addi r4, r0, 4 /* n = 4 */
44 cmpu r4, r4, r7 /* n = c - n (unsigned) */
51 /* n = 4 - n (yields 3, 2, 1 transfers for 1, 2, 3 addr offset) */
[all …]
/Linux-v6.1/fs/xfs/
Dxfs_ondisk.h1 // SPDX-License-Identifier: GPL-2.0
26 XFS_CHECK_STRUCT_SIZE(struct xfs_acl, 4); in xfs_check_ondisk_structs()
32 XFS_CHECK_STRUCT_SIZE(struct xfs_bmbt_rec, 16); in xfs_check_ondisk_structs()
33 XFS_CHECK_STRUCT_SIZE(struct xfs_bmdr_block, 4); in xfs_check_ondisk_structs()
42 XFS_CHECK_STRUCT_SIZE(struct xfs_inobt_key, 4); in xfs_check_ondisk_structs()
43 XFS_CHECK_STRUCT_SIZE(struct xfs_inobt_rec, 16); in xfs_check_ondisk_structs()
44 XFS_CHECK_STRUCT_SIZE(struct xfs_refcount_key, 4); in xfs_check_ondisk_structs()
51 XFS_CHECK_STRUCT_SIZE(xfs_alloc_ptr_t, 4); in xfs_check_ondisk_structs()
53 XFS_CHECK_STRUCT_SIZE(xfs_inobt_ptr_t, 4); in xfs_check_ondisk_structs()
54 XFS_CHECK_STRUCT_SIZE(xfs_refcount_ptr_t, 4); in xfs_check_ondisk_structs()
[all …]
/Linux-v6.1/arch/alpha/include/asm/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
52 srl $16, 6, $16 \n\
53 .align 4 \n\
60 ldq $4,16($17) \n\
61 ldq $5,16($18) \n\
78 xor $4,$5,$4 \n\
82 stq $4,16($17) \n\
93 subq $16,1,$16 \n\
[all …]
/Linux-v6.1/drivers/net/ethernet/aquantia/atlantic/macsec/
Dmacsec_api.c1 // SPDX-License-Identifier: GPL-2.0-only
46 return (*data != 0xffff) ? 0 : -ETIME; in aq_mss_mdio_read()
118 * packed_record - [OUT] The table row data (raw).
269 return -EINVAL; in set_ingress_prectlf_record()
273 packed_record[0] = rec->sa_da[0] & 0xFFFF; in set_ingress_prectlf_record()
274 packed_record[1] = (rec->sa_da[0] >> 16) & 0xFFFF; in set_ingress_prectlf_record()
275 packed_record[2] = rec->sa_da[1] & 0xFFFF; in set_ingress_prectlf_record()
276 packed_record[3] = rec->eth_type & 0xFFFF; in set_ingress_prectlf_record()
277 packed_record[4] = rec->match_mask & 0xFFFF; in set_ingress_prectlf_record()
278 packed_record[5] = rec->match_type & 0xF; in set_ingress_prectlf_record()
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