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/Linux-v5.15/drivers/gpu/drm/exynos/
Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
[all …]
/Linux-v5.15/arch/arm64/crypto/
Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/Linux-v5.15/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/Linux-v5.15/drivers/i3c/master/mipi-i3c-hci/
Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
45 #define CMD_I0_RNW W0_BIT_(29)
[all …]
/Linux-v5.15/sound/soc/fsl/
Dfsl_micfil.h42 #define MICFIL_CTRL1_PDMIEN_SHIFT 29
58 #define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \ argument
84 #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \ argument
90 #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \ argument
100 #define MICFIL_STAT_LOWFREQF_SHIFT 29
103 #define MICFIL_STAT_CHXF_SHIFT(v) (v) argument
104 #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
105 #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
112 #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \ argument
116 #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) argument
[all …]
/Linux-v5.15/drivers/staging/media/hantro/
Dhantro_g1_regs.h134 #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
142 #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
171 #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
311 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
312 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
313 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
314 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0) argument
315 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0) argument
316 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0) argument
317 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0) argument
[all …]
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
/Linux-v5.15/include/linux/spi/
Dmxs-spi.h20 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
/Linux-v5.15/drivers/platform/x86/intel/pmt/
Dcrashlog.c29 * Bits 29 and 30 control the state of bit 31.
31 * Bit 29 will clear bit 31, if set, allowing a new crashlog to be captured.
35 #define CRASHLOG_FLAG_TRIGGER_CLEAR BIT(29)
45 #define GET_ACCESS(v) ((v) & GENMASK(3, 0)) argument
46 #define GET_TYPE(v) (((v) & GENMASK(7, 4)) >> 4) argument
47 #define GET_VERSION(v) (((v) & GENMASK(19, 16)) >> 16) argument
49 #define GET_SIZE(v) ((v) * sizeof(u32)) argument
/Linux-v5.15/drivers/video/fbdev/
Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/Linux-v5.15/drivers/scsi/pm8001/
Dpm80xx_hwi.h125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
343 /* Bits [30:29] - Reserved */
366 u32 reserved[29];
467 u32 reserved[29];
488 u32 reserved1[29];
698 u32 reserved[29];
760 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
824 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
975 u32 reserved[29];
985 __le32 profile[29];
[all …]
/Linux-v5.15/include/dt-bindings/usb/
Dpd.h20 #define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */
102 * <29:27> :: product type (UFP / Cable / VPD)
155 * <31:29> :: UFP VDO version
209 (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \
216 * <31:29> :: DFP VDO version
231 (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \
263 * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
279 * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
446 * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
/Linux-v5.15/arch/powerpc/perf/
Disa207-common.h29 #define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
31 #define EVENT_THRESH_SHIFT 29 /* All threshold bits */
44 #define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK) argument
75 #define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK) argument
78 #define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK) argument
95 #define p10_SDAR_MODE(v) (((v) >> p10_SDAR_MODE_SHIFT) & \ argument
149 #define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56) argument
153 #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32) argument
156 #define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32) argument
159 #define p10_CNST_THRESH_CMP_VAL(v) (((v) & 0x7ffull) << 43) argument
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-au1x00/
Dgpio-au1000.h83 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); in au1500_gpio2_to_irq()
119 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ in au1100_gpio2_to_irq()
156 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); in au1550_gpio2_to_irq()
218 static inline void alchemy_gpio1_set_value(int gpio, int v) in alchemy_gpio1_set_value() argument
221 unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR; in alchemy_gpio1_set_value()
238 static inline int alchemy_gpio1_direction_output(int gpio, int v) in alchemy_gpio1_direction_output() argument
243 alchemy_gpio1_set_value(gpio, v); in alchemy_gpio1_direction_output()
298 static inline void alchemy_gpio2_set_value(int gpio, int v) in alchemy_gpio2_set_value() argument
302 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); in alchemy_gpio2_set_value()
323 static inline int alchemy_gpio2_direction_output(int gpio, int v) in alchemy_gpio2_direction_output() argument
[all …]
/Linux-v5.15/arch/mips/include/asm/netlogic/xlr/
Dfmn.h157 #define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
161 #define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v) argument
162 #define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v) argument
163 #define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v) argument
164 #define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v) argument
165 #define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v) argument
166 #define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v) argument
167 #define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v) argument
168 #define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v) argument
169 #define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v) argument
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/leds/backlight/
Drichtek,rt4831-backlight.yaml44 Backlight OVP level selection, currently support 17V/21V/25V/29V.
/Linux-v5.15/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
70 # 24 chars 29 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
91 # 26 chars 29 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
158 # D: 29.500 MHz, H: 29.738 kHz, V: 60.00 Hz
[all …]
/Linux-v5.15/drivers/hwmon/
Dabituguru3.c191 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
192 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
193 { "MCH 2.5V", 5, 0, 20, 1, 0 },
194 { "ICH 1.05V", 6, 0, 10, 1, 0 },
195 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
196 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
197 { "ATX +5V", 9, 0, 30, 1, 0 },
198 { "+3.3V", 10, 0, 20, 1, 0 },
213 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
214 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
[all …]
/Linux-v5.15/include/linux/usb/
Dpd_vdo.h109 * <29:27> :: product type (UFP / Cable / VPD)
174 * <31:29> :: UFP VDO version
230 (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \
237 * <31:29> :: DFP VDO version
254 (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \
286 * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
302 * <10:9> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
471 * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
/Linux-v5.15/drivers/iio/adc/
Dstm32-dfsdm.h48 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) argument
50 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) argument
52 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) argument
54 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) argument
56 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) argument
58 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) argument
60 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) argument
62 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) argument
64 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) argument
66 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v) argument
[all …]
/Linux-v5.15/arch/powerpc/mm/book3s32/
Dhash_low.S75 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
78 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
82 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
96 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
220 rlwimi r8,r4,22,20,29
323 rlwimi r8,r10,2,29,29
329 SET_V(r5) /* set V (valid) bit */
431 * state with the V bit set.
435 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
442 STPTE r5,0(r4) /* finally set V bit in PTE */
[all …]
/Linux-v5.15/arch/mips/include/asm/
Dmipsmtregs.h93 #define MVPCONF0_TLBS_SHIFT 29
331 #define mttgpr(rd,v) \ argument
341 : : "r" (v)); \
344 #define mttc0(rd, sel, v) \ argument
355 : "r" (v)); \
359 #define mttr(rd, u, sel, v) \ argument
363 : : "r" (v)); \
414 #define read_tc_gpr_sp() mftgpr(29)
415 #define write_tc_gpr_sp(val) mttgpr(29, val)
/Linux-v5.15/arch/x86/kvm/svm/
Dsvm_onhyperv.h3 * KVM L1 hypervisor optimizations on Hyper-V for SVM.
18 * Hyper-V uses the software reserved 32 bytes in VMCB
26 u32 reserved:29;
35 * Hyper-V uses the software reserved clean bit in VMCB
55 pr_info("kvm: Hyper-V enlightened NPT TLB flush enabled\n"); in svm_hv_hardware_setup()
64 pr_info("kvm: Hyper-V Direct TLB Flush enabled\n"); in svm_hv_hardware_setup()
/Linux-v5.15/drivers/media/platform/sti/bdisp/
Dbdisp-reg.h192 #define BLT_INS_AQLOCK BIT(29) /* AQ lock */
204 #define BLT_TTY_VSO BIT(25) /* V scan order */
212 #define BLT_S1TY_RGB_EXP BIT(29) /* RGB expansion mode */
217 #define BLT_S2TY_RGB_EXP BIT(29) /* RGB expansion mode */
221 #define BLT_FCTL_HV_SCALE 0x00000055 /* H/V resize + color filter */
224 #define BLT_FCTL_HV_SAMPLE 0x00000044 /* H/V resize */
/Linux-v5.15/tools/testing/selftests/powerpc/include/
Dreg.h15 #define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \ argument
16 : "r" ((unsigned long)(v)) \
60 #define set_amr(v) asm volatile("isync;" \ argument
63 : "r" ((unsigned long)(v)) \
118 "li 29, %[" #_asm_symbol_name_immed "];" \
152 "lfs 29, 0(%[" #_asm_symbol_name_addr "]);" \

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