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/Linux-v5.15/drivers/staging/media/hantro/
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
Dhantro_g1_regs.h50 #define G1_REG_DEC_CTRL0_DIVX3_E BIT(25)
84 #define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25)
127 #define G1_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25)
137 #define G1_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25)
156 #define G1_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25)
204 #define G1_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25)
217 #define G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25)
258 #define G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25)
276 #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25)
311 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
Dhantro_g1_mpeg2_dec.c25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
[all …]
/Linux-v5.15/arch/arm64/crypto/
Dsha512-ce-core.S85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
101 sha512h2 q\i3, q\i1, v\i0\().2d
[all …]
/Linux-v5.15/drivers/net/wan/
DKconfig9 Wide Area Networks (WANs), such as X.25, Frame Relay and leased
46 base-band modems, or any other device with the X.21, V.24, V.35 or
47 V.36 interface) to your Linux box. The cards can work as the
64 tristate "LanMedia Corp. SSI/V.35, T1/E1, HSSI, T3 boards"
71 V.24, V.35 or V.36 interface) to your Linux box.
109 Relay, synchronous Point-to-Point Protocol (PPP) and X.25.
160 tristate "X.25 protocol support"
163 Generic HDLC driver supporting X.25 over WAN connections.
167 comment "X.25/LAPB support is disabled"
255 Support for the FarSync T-Series X.21 (and V.35/V.24) cards by
[all …]
/Linux-v5.15/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
87 # 13 chars 25 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
[all …]
/Linux-v5.15/arch/arm64/kvm/hyp/
Daarch32.c32 0xAAAA, /* VS == V set */
36 0xAA55, /* GE == (N==V) */
37 0x55AA, /* LT == (N!=V) */
38 0x0A05, /* GT == (!Z && (N==V)) */
39 0xF5FA, /* LE == (Z || (N!=V)) */
68 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); in kvm_condition_valid32()
94 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
107 itbits |= (cpsr & (0x3 << 25)) >> 25; in kvm_adjust_itstate()
118 cpsr |= (itbits & 0x3) << 25; in kvm_adjust_itstate()
/Linux-v5.15/drivers/ata/
Dlibata-pata-timings.c31 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 },
32 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 },
41 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
42 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
43 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 },
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1) argument
58 #define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0) argument
/Linux-v5.15/include/linux/spi/
Dmxs-spi.h24 #define BM_SSP_CTRL0_READ (1 << 25)
36 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
71 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
[all …]
/Linux-v5.15/drivers/hwmon/
Dabituguru3.c191 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
192 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
193 { "MCH 2.5V", 5, 0, 20, 1, 0 },
194 { "ICH 1.05V", 6, 0, 10, 1, 0 },
195 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
196 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
197 { "ATX +5V", 9, 0, 30, 1, 0 },
198 { "+3.3V", 10, 0, 20, 1, 0 },
201 { "System", 25, 1, 1, 1, 0 },
213 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
[all …]
/Linux-v5.15/include/linux/
Dinet.h12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
21 * $Id: ip.c,v 0.8.4.8 1992/12/12 19:25:04 bir7 Exp $
[all …]
/Linux-v5.15/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/Linux-v5.15/drivers/i3c/master/mipi-i3c-hci/
Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v) argument
[all …]
/Linux-v5.15/lib/crypto/
Dcurve25519-fiat32.c20 * fe limbs are bounded by 1.125*2^26,1.125*2^25,1.125*2^26,1.125*2^25,etc.
23 typedef struct fe { u32 v[10]; } fe; member
25 /* fe_loose limbs are bounded by 3.375*2^26,3.375*2^25,3.375*2^26,3.375*2^25,etc
28 typedef struct fe_loose { u32 v[10]; } fe_loose; member
42 h[1] = (a0>>26) | ((a1&((1<<19)-1))<< 6); /* (32-26) + 19 = 6+19 = 25 */ in fe_frombytes_impl()
44 h[3] = (a2>>13) | ((a3&((1<< 6)-1))<<19); /* (32-13) + 6 = 19+ 6 = 25 */ in fe_frombytes_impl()
46 h[5] = a4&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
47 h[6] = (a4>>25) | ((a5&((1<<19)-1))<< 7); /* (32-25) + 19 = 7+19 = 26 */ in fe_frombytes_impl()
48 h[7] = (a5>>19) | ((a6&((1<<12)-1))<<13); /* (32-19) + 12 = 13+12 = 25 */ in fe_frombytes_impl()
50 h[9] = (a7>> 6)&((1<<25)-1); /* 25 */ in fe_frombytes_impl()
[all …]
/Linux-v5.15/tools/testing/selftests/drivers/net/mlxsw/
Dtc_sample.sh62 ip -4 route add default vrf v$h1 nexthop via 192.0.2.2
67 ip -4 route del default vrf v$h1 nexthop via 192.0.2.2
76 ip -4 route add default vrf v$h2 nexthop via 198.51.100.2
81 ip -4 route del default vrf v$h2 nexthop via 198.51.100.2
94 ip -4 route add default vrf v${h3}_bond nexthop via 192.0.2.18
99 ip -4 route del default vrf v${h3}_bond nexthop via 192.0.2.18
115 ip -4 route add default vrf v${h4}_bond nexthop via 198.51.100.18
120 ip -4 route del default vrf v${h4}_bond nexthop via 198.51.100.18
237 ip vrf exec v$h1 $MZ $h1 -c 320000 -d 100usec -p 64 -A 192.0.2.1 \
244 (( -25 <= pct && pct <= 25))
[all …]
/Linux-v5.15/drivers/clk/versatile/
Dclk-icst.c74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
89 * access the low eight bits of the v PLL divider. Bit 8 is tied low in vco_get()
96 vco->v = val & INTEGRATOR_AP_SYS_BITS; in vco_get()
106 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the in vco_get()
107 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies in vco_get()
108 * 33 or 25 MHz respectively. in vco_get()
113 vco->v = divxy ? 17 : 14; in vco_get()
121 * of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
128 vco->v = val & 0xFF; in vco_get()
[all …]
/Linux-v5.15/drivers/net/hamradio/
Dbpqether.c3 * G8BPQ compatible "AX.25 via ethernet" driver release 004
7 * This is a "pseudo" network driver to allow AX.25 over Ethernet
15 * - user-level programs like the AX.25 utilities shouldn't
17 * - IP over ethernet encapsulated AX.25 was impossible
38 * BPQ 001 Joerg(DL1BKE) Extracted BPQ code from AX.25
85 "AX.25: bpqether driver version 004\n";
168 * Receive an AX.25 frame via an ethernet interface.
236 * Send an AX.25 frame via an ethernet interface
299 * Set AX.25 callsign
394 static void *bpq_seq_next(struct seq_file *seq, void *v, loff_t *pos) in bpq_seq_next() argument
[all …]
/Linux-v5.15/drivers/net/ethernet/altera/
Daltera_tse.h52 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
72 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
79 #define MAC_CMDCFG_ENA_10 BIT(25)
84 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
85 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
86 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) argument
87 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) argument
88 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) argument
89 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) argument
90 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) argument
[all …]
/Linux-v5.15/sound/soc/fsl/
Dfsl_micfil.h58 #define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \ argument
69 #define MICFIL_CTRL2_QSEL_SHIFT 25
84 #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \ argument
90 #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \ argument
103 #define MICFIL_STAT_CHXF_SHIFT(v) (v) argument
104 #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
105 #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) argument
112 #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \ argument
116 #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) argument
117 #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)) argument
[all …]
Dfsl_xcvr.h78 #define FSL_XCVR_EXT_CTRL_DMA_RD_DIS BIT(25)
80 #define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25))
104 #define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25)
154 #define FSL_XCVR_PHY_AI_TOG_DONE_PLL BIT(25)
179 #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE BIT(25)
223 #define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25)
225 #define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i)) argument
233 #define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25)
234 #define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25)
/Linux-v5.15/arch/mips/include/asm/netlogic/xlr/
Dfmn.h153 #define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
161 #define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v) argument
162 #define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v) argument
163 #define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v) argument
164 #define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v) argument
165 #define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v) argument
166 #define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v) argument
167 #define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v) argument
168 #define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v) argument
169 #define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v) argument
[all …]
/Linux-v5.15/Documentation/userspace-api/media/dvb/
Dca_high_level.rst106 (25) ES type=[4] ES pid=[301] ES length =[0 (0x0)]
107 ca_message length is 25 (0x19) bytes
136 v
141 | v |
145 | v |
149 | v |
154 v
/Linux-v5.15/Documentation/devicetree/bindings/leds/backlight/
Drichtek,rt4831-backlight.yaml44 Backlight OVP level selection, currently support 17V/21V/25V/29V.
/Linux-v5.15/drivers/media/platform/
Dimx-pxp.h19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
[all …]

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