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/Linux-v5.15/arch/powerpc/lib/
Dtest_emulate_step.c964 .instr = ppc_inst(PPC_RAW_ADD(20, 21, 22)),
966 .gpr[21] = LONG_MIN,
972 .instr = ppc_inst(PPC_RAW_ADD(20, 21, 22)),
974 .gpr[21] = LONG_MIN,
980 .instr = ppc_inst(PPC_RAW_ADD(20, 21, 22)),
982 .gpr[21] = LONG_MAX,
988 .instr = ppc_inst(PPC_RAW_ADD(20, 21, 22)),
990 .gpr[21] = ULONG_MAX,
996 .instr = ppc_inst(PPC_RAW_ADD(20, 21, 22)),
998 .gpr[21] = ULONG_MAX,
[all …]
/Linux-v5.15/drivers/video/logo/
Dlogo_superh_clut224.ppm434 238 182 14 234 190 10 234 196 18 238 202 21
474 234 190 10 238 202 21 244 212 20 246 218 74
514 238 202 21 244 212 20 244 212 20 244 212 20
534 238 202 21 234 196 18 214 174 14 190 146 14
1161 238 202 21 234 196 18 82 82 82 34 34 34
1291 246 190 14 240 198 14 240 198 14 238 202 21
1343 231 220 218 254 21 21 254 3 3 254 3 3
1348 254 3 3 254 3 3 254 3 3 254 21 21
1349 226 210 207 226 210 207 254 21 21 254 21 21
1350 254 21 21 254 21 21 239 159 153 252 251 251
[all …]
Dlogo_spe_clut224.ppm7 15 15 15 21 21 21 19 19 19 14 14 14 6 6 6 2 2 2
13 0 0 0 0 0 0 0 0 0 2 2 2 21 21 21 55 55 55
49 3 3 6 2 2 6 2 2 6 15 15 15 21 21 21 7 7 10
83 0 0 0 5 5 5 59 59 59 21 21 21 175 122 13 231 174 11
127 244 244 244 19 19 21 2 2 6 2 2 6 2 2 6 38 38 38
145 0 0 0 0 0 0 0 0 0 6 6 6 59 59 59 19 19 21
152 0 0 0 0 0 0 0 0 0 16 16 16 67 67 67 19 19 21
173 0 0 0 4 4 4 39 39 39 42 42 43 19 19 21 13 13 13
261 189 138 9 126 107 64 59 59 59 21 21 21 5 5 5 0 0 0
279 21 21 21 33 33 33 31 31 31 16 16 16 2 2 2 0 0 0
/Linux-v5.15/tools/testing/selftests/tc-testing/tc-tests/actions/
Dbpf.json17 …"cmdUnderTest": "$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0'…
20 …"matchPattern": "action order [0-9]*: bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0' …
124 … "$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0' index 555",
130 …"cmdUnderTest": "$TC action replace action bpf bytecode '4,40 0 0 12,21 0 1 2054,6 0 0 262144,6 0 …
133 …"matchPattern": "action order [0-9]*: bpf bytecode '4,40 0 0 12,21 0 1 2054,6 0 0 262144,6 0 0 0' …
154 … "$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0' index 444",
163 …"matchPattern": "action order [0-9]*: bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0' …
183 … "$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 2048,6 0 0 262144,6 0 0 0' ok index 101",
184 …"$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 2054,6 0 0 262144,6 0 0 0' drop index 102",
185 …"$TC action add action bpf bytecode '4,40 0 0 12,21 0 1 33024,6 0 0 262144,6 0 0 0' continue index…
[all …]
/Linux-v5.15/arch/arm/lib/
Dcopy_template.S165 ldr1b r1, r3, ne, abort=21f
166 ldr1b r1, r4, cs, abort=21f
167 ldr1b r1, ip, cs, abort=21f
168 str1b r0, r3, ne, abort=21f
169 str1b r0, r4, cs, abort=21f
170 str1b r0, ip, cs, abort=21f
176 ldr1b r1, r3, gt, abort=21f
177 ldr1b r1, r4, ge, abort=21f
178 ldr1b r1, lr, abort=21f
179 str1b r0, r3, gt, abort=21f
[all …]
/Linux-v5.15/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_init_ops.h344 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
345 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
346 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
347 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
348 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
349 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
350 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
351 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
352 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
353 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
[all …]
/Linux-v5.15/arch/alpha/include/asm/
Dxor.h48 ldq $21,40($17) \n\
67 xor $21,$22,$21 \n\
71 stq $21,40($17) \n\
99 ldq $21,24($17) \n\
114 xor $21,$22,$22 # 5 cycles from $22 load \n\
179 ldq $21,16($17) \n\
196 xor $21,$22,$22 # 7 cycles from $22 load \n\
211 ldq $21,40($19) \n\
235 xor $21,$22,$22 # 8 cycles from $22 load \n\
271 ldq $4,0($21) \n\
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/dsi/
Dsfpb.xml.h11 …sa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
17 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
Dmmss_cc.xml.h11 …sa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
17 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
Ddsi_phy_10nm.xml.h11 …sa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
17 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
/Linux-v5.15/drivers/gpu/drm/msm/hdmi/
Dqfprom.xml.h11 …sa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
17 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
/Linux-v5.15/Documentation/translations/zh_CN/core-api/
Dcpu_hotplug.rst101 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
102 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
103 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
104 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
105 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
106 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
107 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu6
108 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu7
109 drwxr-xr-x 2 root root 0 Dec 21 16:33 hotplug
110 -r--r--r-- 1 root root 4.0K Dec 21 16:33 offline
[all …]
/Linux-v5.15/drivers/mtd/maps/
Dphysmap-gemini.c35 #define FLASH_SIZE_MASK (0x3 << 21)
36 #define NAND_256M (0x3 << 21) /* and more */
37 #define NAND_128M (0x2 << 21)
38 #define NAND_64M (0x1 << 21)
39 #define NAND_32M (0x0 << 21)
40 #define ATMEL_16M (0x3 << 21) /* and more */
41 #define ATMEL_8M (0x2 << 21)
42 #define ATMEL_4M_2M (0x1 << 21)
43 #define ATMEL_1M (0x0 << 21) /* and less */
/Linux-v5.15/drivers/gpu/drm/msm/disp/
Dmdp_common.xml.h11 …sa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
17 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 …sa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
/Linux-v5.15/Documentation/RCU/Design/Data-Structures/
DTreeLevel.svg157 style="fill:#000000;stroke:#000000;stroke-width:21;"
164 style="fill:#000000;stroke:#000000;stroke-width:21;"
171 style="fill:#000000;stroke:#000000;stroke-width:21;"
190 style="fill:#000000;stroke:#000000;stroke-width:21;"
197 style="fill:#000000;stroke:#000000;stroke-width:21;"
204 style="fill:#000000;stroke:#000000;stroke-width:21;"
211 style="fill:#000000;stroke:#000000;stroke-width:21;"
218 style="fill:#000000;stroke:#000000;stroke-width:21;"
225 style="fill:#000000;stroke:#000000;stroke-width:21;"
232 style="fill:#000000;stroke:#000000;stroke-width:21;"
[all …]
DHugeTreeClassicRCU.svg157 style="fill:#000000;stroke:#000000;stroke-width:21;"
164 style="fill:#000000;stroke:#000000;stroke-width:21;"
171 style="fill:#000000;stroke:#000000;stroke-width:21;"
190 style="fill:#000000;stroke:#000000;stroke-width:21;"
197 style="fill:#000000;stroke:#000000;stroke-width:21;"
204 style="fill:#000000;stroke:#000000;stroke-width:21;"
211 style="fill:#000000;stroke:#000000;stroke-width:21;"
218 style="fill:#000000;stroke:#000000;stroke-width:21;"
225 style="fill:#000000;stroke:#000000;stroke-width:21;"
232 style="fill:#000000;stroke:#000000;stroke-width:21;"
[all …]
/Linux-v5.15/include/soc/mscc/
Docelot_sys.h40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
97 #define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))
98 #define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)
99 #define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)
/Linux-v5.15/drivers/staging/rtl8723bs/include/
Drtw_ht.h96 …CEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
97 …ANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
98 …MP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
99 …MP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
100 …ING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
102 #define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, …
103 #define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, …
/Linux-v5.15/arch/arm/boot/dts/
Dimx6qp.dtsi22 pre1: pre@21c8000 {
31 pre2: pre@21c9000 {
40 pre3: pre@21ca000 {
49 pre4: pre@21cb000 {
58 prg1: prg@21cc000 {
67 prg2: prg@21cd000 {
/Linux-v5.15/arch/arm/mach-omap1/
Dmux.c26 MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
34 MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
37 MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
61 MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
76 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
82 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
125 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
156 MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
176 MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
183 MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dmpc834x_mds.dts288 0x8800 0x0 0x0 0x2 &ipic 21 0x8
296 0x9000 0x0 0x0 0x4 &ipic 21 0x8
301 0x9800 0x0 0x0 0x3 &ipic 21 0x8
306 0xa800 0x0 0x0 0x2 &ipic 21 0x8
313 0xb000 0x0 0x0 0x3 &ipic 21 0x8
320 0xb800 0x0 0x0 0x4 &ipic 21 0x8
323 0xc000 0x0 0x0 0x1 &ipic 21 0x8
349 0x8800 0x0 0x0 0x2 &ipic 21 0x8
357 0x9000 0x0 0x0 0x4 &ipic 21 0x8
362 0x9800 0x0 0x0 0x3 &ipic 21 0x8
[all …]
/Linux-v5.15/drivers/gpu/drm/mxsfb/
Dmxsfb_regs.h59 #define CTRL1_FIFO_CLEAR BIT(21)
66 #define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21)
67 #define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21)
68 #define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21)
69 #define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21)
70 #define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21)
82 #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
/Linux-v5.15/Documentation/userspace-api/media/v4l/
Dpixfmt-yuv-planar.rst199 - Y'\ :sub:`21`
234 - Y'\ :sub:`21`
325 - Y'\ :sub:`21`
346 - Cb\ :sub:`21`
347 - Cr\ :sub:`21`
370 - Y'\ :sub:`21`
428 - Y'\ :sub:`21`
457 - Cb\ :sub:`21`
458 - Cr\ :sub:`21`
622 - Y'\ :sub:`21`
[all …]
/Linux-v5.15/arch/arm/kernel/
Dphys2virt.S41 mov r0, r3, lsr #21 @ constant for add/sub instructions
42 teq r3, r0, lsl #21 @ must be 2 MiB aligned
63 @ phys-to-virt: movw <reg>, #offset<31:21>
64 @ lsl <reg>, #21
67 @ virt-to-phys (non-LPAE): movw <reg>, #offset<31:21>
68 @ lsl <reg>, #21
71 @ virt-to-phys (LPAE): movw <reg>, #offset<31:21>
72 @ lsl <reg>, #21
103 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
105 ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field
/Linux-v5.15/include/linux/platform_data/
Dvideo-ep93xx.h28 #define EP93XXFB_USE_SDCSN0 (0 << 21)
29 #define EP93XXFB_USE_SDCSN1 (1 << 21)
30 #define EP93XXFB_USE_SDCSN2 (2 << 21)
31 #define EP93XXFB_USE_SDCSN3 (3 << 21)

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