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/Linux-v6.1/arch/arm64/crypto/
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
21 * ARMv8.2 Crypto Extensions instructions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
[all …]
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
8 // it under the terms of the GNU General Public License version 2 as
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
26 // General Public License (GPL) Version 2, available from the file
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
110 movi k32_48.2d, #0xffffffff
111 mov k32_48.h[2], k32_48.h[0]
112 ushr k00_16.2d, k32_48.2d, #32
116 movi perm4.8b, #8
[all …]
/Linux-v6.1/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
/Linux-v6.1/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
33 * Component 2: B
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
[all …]
/Linux-v6.1/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
[all …]
/Linux-v6.1/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/disp/
Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
89 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
91 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
93 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
95 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
97 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
99 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
101 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
103 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
105 FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
[all …]
/Linux-v6.1/drivers/media/test-drivers/vicodec/
Dcodec-fwht.c1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
21 * be guaranteed that the magic 8 byte sequence (see below) can
34 1, 8,
35 2, 9, 16,
57 s16 block[8 * 8]; in rlc()
67 for (y = 0; y < 8; y++) { in rlc()
68 for (x = 0; x < 8; x++) { in rlc()
[all …]
/Linux-v6.1/arch/arm/mach-davinci/
Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
15 #include <linux/platform_data/gpio-davinci.h>
17 #include <clocksource/timer-davinci.h>
27 /* Offsets of the 8 compare registers on the da830 */
48 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
50 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
51 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
53 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
[all …]
/Linux-v6.1/arch/arm/mach-omap1/
Dopp_data.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/opp_data.c
5 * Copyright (C) 2004 - 2005 Nokia corporation
13 /*-------------------------------------------------------------------------
15 *-------------------------------------------------------------------------*/
21 { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
23 { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
25 { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
27 { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
29 { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
[all …]
/Linux-v6.1/drivers/pinctrl/mediatek/
Dpinctrl-mt8173.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt8173.h"
22 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
24 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
25 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
27 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
[all …]
Dpinctrl-mt2712.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/pinctrl/pinconf-generic.h>
15 #include <dt-bindings/pinctrl/mt65xx.h>
17 #include "pinctrl-mtk-common.h"
18 #include "pinctrl-mtk-mt2712.h"
21 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
25 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
26 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
30 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
[all …]
/Linux-v6.1/arch/mips/kernel/
Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
55 extern const unsigned int fpucondbit[8];
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
[all …]
/Linux-v6.1/drivers/video/fbdev/
Datafb_iplan2p8.c2 * linux/drivers/video/iplan2p8.c -- Low level frame buffer operations for
3 * interleaved bitplanes à la Atari (8
4 * planes, 2 bytes interleave)
20 #define BPL 8
24 /* Copies a 8 plane column from 's', height 'h', to 'd'. */
26 /* This expands a 8 bit color into two longs for two movepl (8 plane)
54 /* odd->odd or even->even */ in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
60 memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2); in atafb_iplan2p8_copyarea()
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dsc/
Drc_calc_fpu.c31 #define table_hash(mode, bpc, max_min) ((mode << 16) | (bpc << 8) | max_min)
57 num = num - 0.5; in dsc_roundf()
76 TABLE_CASE(444, 8, max); in get_qp_set()
77 TABLE_CASE(444, 8, min); in get_qp_set()
82 TABLE_CASE(422, 8, max); in get_qp_set()
83 TABLE_CASE(422, 8, min); in get_qp_set()
88 TABLE_CASE(420, 8, max); in get_qp_set()
89 TABLE_CASE(420, 8, min); in get_qp_set()
99 index = (bpp - table[0].bpp) * 2; in get_qp_set()
115 …8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (0 + dsc_roundf((b… in get_ofs_set()
[all …]
/Linux-v6.1/drivers/input/misc/
Dyealink.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 u8 size; /* 1-11, size of used data bytes. */
49 * offset key number [0-1f]
57 * size 1-11
58 * offset 0-23
77 * data[0] 0-0xff volume
84 * size 1-11
85 * offset 0->
86 * data binary representation LE16(-freq), LE16(duration) ....
139 _SEG('1', 0,0 , 22,2 , 22,2 , 0,0 , 0,0 , 0,0 , 0,0 ),
[all …]
/Linux-v6.1/include/asm-generic/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-generic/xor.h
5 * Generic optimized RAID-5 checksumming functions.
14 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_2()
19 p1[2] ^= p2[2]; in xor_8regs_2()
25 p1 += 8; in xor_8regs_2()
26 p2 += 8; in xor_8regs_2()
27 } while (--lines > 0); in xor_8regs_2()
35 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_3()
40 p1[2] ^= p2[2] ^ p3[2]; in xor_8regs_3()
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
33 { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
35 { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
37 { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
39 { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
41 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
43 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
44 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
45 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
46 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
[all …]
Dintel_vdsc.c1 // SPDX-License-Identifier: MIT
61 /* 6BPP/8BPC */
63 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
64 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
65 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
66 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
71 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
72 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
73 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
74 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
[all …]
/Linux-v6.1/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dtie.h9 * Copyright (C) 1999-2009 Tensilica Inc.
16 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
24 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
43 /* Save area for non-coprocessor optional and custom (TIE) state: */
48 #define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
49 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
61 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
62 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
65 * galign = group byte alignment (power of 2) (galign >= align)
66 * align = register byte alignment (power of 2)
[all …]
/Linux-v6.1/Documentation/admin-guide/media/
Ddvb_intro.rst1 .. SPDX-License-Identifier: GPL-2.0
12 structure of DVB-T cards are substantially similar to Analogue TV cards,
30 embedded within the modulated composite analogue signal -
38 signal encoded at a resolution of 768x576 24-bit color pixels over 25
39 frames per second - a fair amount of data is generated and must be
43 encoded and compressed form - similar to the form that is used in
46 The purpose of a simple budget digital TV card (DVB-T,C or S) is to
96 On this example, we're considering tuning into DVB-T channels in
115 The digital TV Scan utilities (like dvbv5-scan) have use a set of
116 compiled-in defaults for various countries and regions. Those are
[all …]
/Linux-v6.1/drivers/media/dvb-frontends/
Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define STV090x_WIDTH_DACR2_VALUE_FIELD 8
48 #define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2
66 #define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2
76 #define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2
94 #define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2
108 #define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
126 #define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2
144 #define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2
162 #define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2
[all …]
/Linux-v6.1/arch/powerpc/crypto/
Daes-spe-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "aes-spe-regs.h"
17 rlwimi rT0,in,28-((bpos+3)%4)*8,20,27;
20 rlwimi rT1,in,24-((bpos+3)%4)*8,24,31;
41 LBZ(out, rT0, 8)
44 LBZ(out, rT0, 8) /* load enc byte */
56 * via bl/blr. It expects that caller has pre-xored input data with first
57 * 4 words of encryption key into rD0-rD3. Pointer/counter registers must
58 * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
59 * and rW0-rW3 and caller must execute a final xor on the output registers.
[all …]
/Linux-v6.1/tools/testing/selftests/powerpc/copyloops/
Dmemcpy_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
13 /* For big-endian, 0 == most CPUs, 1 == POWER6, 2 == Cell */
23 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1) /* save destination pointer for return value */
31 /* dumb little-endian memcpy that will get replaced at runtime */
32 addi r9,r3,-1
33 addi r4,r4,-1
43 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
60 addi r3,r3,-16
[all …]
/Linux-v6.1/arch/powerpc/lib/
Dmemcpy_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
13 /* For big-endian, 0 == most CPUs, 1 == POWER6, 2 == Cell */
23 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1) /* save destination pointer for return value */
31 /* dumb little-endian memcpy that will get replaced at runtime */
32 addi r9,r3,-1
33 addi r4,r4,-1
43 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
60 addi r3,r3,-16
[all …]

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