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/Linux-v6.1/Documentation/translations/zh_CN/core-api/
Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
[all …]
/Linux-v6.1/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
32 This API deals with 2 basic operations:
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
[all …]
/Linux-v6.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7629.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "pinctrl-moore.h"
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
45 PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
55 PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
65 PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
75 PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
85 PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
95 PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
117 MT7629_PIN(2, "WF0_5G_HB0", 55),
[all …]
Dpinctrl-mt8183.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "pinctrl-mtk-mt8183.h"
10 #include "pinctrl-paris.h"
13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
50 PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1),
51 PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1),
52 PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1),
53 PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1),
54 PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1),
55 PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1),
[all …]
/Linux-v6.1/arch/mips/include/asm/octeon/
Dcvmx-address.h7 * Copyright (c) 2003-2009 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
38 CVMX_MIPS_SPACE_XKPHYS = 2LL,
47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
56 CVMX_ADD_WIN_UNUSED = 2L,
71 CVMX_ADD_WIN_DMA_SENDDMA = 2L,
76 /* send out a single-tick command on the NCB bus */
84 * Octeon-I HW never interprets this X (<39:36> reserved
[all …]
/Linux-v6.1/arch/arm/mach-davinci/
Dirqs.h8 * Free Software Foundation; either version 2 of the License, or (at your
36 #define IRQ_VDINT2 2
82 #define IRQ_GPIO1 49
102 /* DaVinci DM6467-specific Interrupts */
105 #define IRQ_DM646X_VP_VERTINT2 2
139 #define IRQ_DM646X_GPIO1 49
152 /* DaVinci DM355-specific Interrupts */
155 #define IRQ_DM355_CCDC_VDINT2 2
190 #define IRQ_DM355_GPIO5 49
203 /* DaVinci DM365-specific Interrupts */
[all …]
/Linux-v6.1/drivers/staging/media/ipu3/
Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
18 .sample_patrn_length = 2,
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/Linux-v6.1/arch/arm/mach-mmp/
Dirqs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define IRQ_PXA168_NONE (-1)
11 #define IRQ_PXA168_SSP2 2
48 #define IRQ_PXA168_GPIOX 49
58 #define IRQ_PXA910_NONE (-1)
61 #define IRQ_PXA910_SSP2 2
108 #define IRQ_PXA910_AP_GPIO 49
120 #define IRQ_MMP2_NONE (-1)
123 #define IRQ_MMP2_SSPA1 2
166 #define IRQ_MMP2_GPIO 49
[all …]
/Linux-v6.1/drivers/net/appletalk/
Dcops_ffdrv.h24 * - Jay Schulist <jschlst@samba.org>
36 237,57,49,33,107,137,34,32,128,33,83,130,
41 105,103,104,116,32,40,67,41,32,49,57,56,
48 0,4,96,10,224,6,0,7,126,2,64,11,
57 2,219,96,33,233,149,119,230,62,33,232,149,
63 58,72,152,183,32,26,6,20,17,128,2,237,
75 225,193,241,251,237,77,33,2,0,57,126,230,
76 3,237,100,1,40,2,246,128,230,130,245,62,
82 49,152,119,219,72,43,43,112,17,3,0,237,
88 255,202,128,132,58,49,152,254,161,250,207,131,
[all …]
Dcops_ltdrv.h23 * - Jay Schulist <jschlst@samba.org>
35 62,12,237,57,49,62,195,33,39,2,50,56,
36 0,34,57,0,237,86,205,30,2,251,205,60,
38 32,40,99,41,32,49,57,56,56,45,49,57,
45 4,96,10,224,6,0,7,126,2,64,11,246,
52 2,33,39,2,34,64,0,58,3,0,230,1,
55 150,10,14,83,17,98,2,67,20,237,162,58,
66 83,17,98,2,67,20,58,178,1,95,195,59,
67 2,62,129,190,194,227,2,54,130,43,70,58,
69 254,2,35,35,126,254,132,194,227,2,205,61,
[all …]
/Linux-v6.1/include/dt-bindings/clock/
Dmt2701-clk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define CLK_TOP_SYSPLL_D2 2
59 #define CLK_TOP_TVDPLL_D4 49
176 #define CLK_APMIXED_MAINPLL 2
194 #define CLK_DDRPHY_NR 2
199 #define CLK_INFRA_SMI 2
223 #define CLK_PERI_THERM 2
272 #define CLK_PERI_NR 49
277 #define CLK_AUD_LRCK_DETECT 2
326 #define CLK_AUD_MMIF_DLMCH 49
[all …]
Dimx8ulp-clock.h1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
56 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49
69 #define IMX8ULP_CLK_PLL4_VCODIV 2
117 #define IMX8ULP_CLK_CGC2_END 49
122 #define IMX8ULP_CLK_LPIT1 2
174 #define IMX8ULP_CLK_TPM7 2
201 #define IMX8ULP_CLK_SAI7 2
248 #define IMX8ULP_CLK_DMA2_CH29 49
Dmt7986-clk.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
14 #define CLK_APMIXED_MMPLL 2
25 #define CLK_TOP_RTC_32K 2
72 #define CLK_TOP_A1SYS_SEL 49
92 #define CLK_INFRA_UART1_SEL 2
139 #define CLK_INFRA_IUSB_SYS_CK 49
151 #define CLK_SGMII0_CDR_REF 2
158 #define CLK_SGMII1_CDR_REF 2
165 #define CLK_ETH_GP1_EN 2
Dpistachio-clk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define CLK_RPU_V_PLL 2
18 /* Fixed-factor clocks */
40 #define CLK_UART1 49
110 #define PERIPH_CLK_DDR 2
141 #define PERIPH_CLK_I2C2_DIV 49
150 #define SYS_CLK_I2C2 2
178 #define EXT_CLK_NR_CLKS 2
Dmt6779-clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define CLK_TOP_MM 2
59 #define CLK_TOP_MAINPLL_D2_D4 49
167 #define CLK_APMIXED_ARMPLL_BL 2
194 #define CLK_CAM_DFP_VAD 2
210 #define CLK_INFRA_PMIC_AP 2
257 #define CLK_INFRA_CCIF_MD 49
320 #define CLK_MFGCFG_NR_CLK 2
324 #define CLK_IMG_MFB 2
332 #define CLK_IPE_LARB8 2
[all …]
/Linux-v6.1/drivers/media/v4l2-core/
Dv4l2-vp9.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <media/v4l2-vp9.h>
46 { 55, 27, 12, 153, 203, 218, 26, 27, 49 }, /*left = d207*/
47 { 53, 49, 21, 110, 116, 168, 59, 80, 76 }, /*left = d63 */
72 { 64, 19, 37, 156, 66, 138, 49, 95, 133 }, /*left = dc */
80 { 45, 26, 28, 129, 45, 129, 49, 147, 123 }, /*left = d63 */
92 { 37, 49, 25, 129, 168, 164, 41, 54, 148 }, /*left = tm */
99 { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/
120 { 49, 50, 35, 144, 95, 205, 63, 78, 59 }, /*left = d135*/
131 /* 8x8 -> 4x4 */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_flat_memory.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
57 * System Unified Address - SUA
81 * HSA64 - ATC/IOMMU 64b
101 * 64b to 49b Address conversion
106 * to a 49b address. This 49b address is constituted of an “ATC” bit
107 * plus a 48b virtual address. This 49b address is what is passed to the
109 * (max of 2^40 – 1) intended to be translated via GPUVM page tables.
116 * as part of the 64b to 49b conversion.
118 * Where this 64b to 49b conversion is done is a function of the usage.
[all …]
/Linux-v6.1/drivers/staging/r8188eu/hal/
DHal8188ERateAdaptive.c1 // SPDX-License-Identifier: GPL-2.0
7 {5, 4, 3, 2, 0, 3}, /* 92 , idx = 0 */
9 {6, 5, 4, 2, 0, 4}, /* 81 , idx = 2 */
13 {10, 9, 8, 2, 0, 8}, /* 62 , idx = 6 */
23 {49, 46, 40, 16, 0, 48}, /* 20 , idx = 0x10 */
24 {49, 45, 32, 0, 0, 48}, /* 17 , idx = 0x11 */
25 {49, 45, 22, 18, 0, 48}, /* 15 , idx = 0x12 */
26 {49, 40, 24, 16, 0, 48}, /* 12 , idx = 0x13 */
27 {49, 32, 18, 12, 0, 48}, /* 9 , idx = 0x14 */
28 {49, 22, 18, 14, 0, 48}, /* 6 , idx = 0x15 */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dsprd,spi-adi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 ADI is the abbreviation of Anolog-Digital interface, which is used to access
21 ADI controller has 50 channels including 2 software read/write channels and
22 48 hardware channels to access analog chip. For 2 software read/write channels,
[all …]
/Linux-v6.1/drivers/video/fbdev/i810/
Di810_gtf.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_main.h -- Intel 810 Non-discrete Video Timings
20 * FIFO and Watermark tables - based almost wholly on i810_wmark.c in
33 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
47 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
61 { 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
74 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
88 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
102 { 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
116 * i810fb_encode_registers - encode @var to hardware register values
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/Linux-v6.1/drivers/staging/media/rkvdec/
Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
46 #define CHROMA_FORMAT_IDC PS_FIELD(13, 2)
52 #define PIC_ORDER_CNT_TYPE PS_FIELD(31, 2)
61 #define NUM_VIEWS PS_FIELD(60, 2)
73 #define WEIGHTED_BIPRED_IDC PS_FIELD(154, 2)
93 s8 cabac_table[4][464][2];
[all …]
/Linux-v6.1/drivers/mfd/
Dqcom_rpm.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <dt-bindings/mfd/qcom-rpm.h>
58 #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
59 #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
60 #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
92 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
93 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
94 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
95 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
96 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[all …]
/Linux-v6.1/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only
33 #define OTX2_CPT_LF_MSIX_VECTORS 2
147 * OcteonTX2 CPT VF MSI-X Vector Enumeration
148 * Enumerates the MSI-X interrupt vectors.
157 * OcteonTX2 CPT LF MSI-X Vector Enumeration
158 * Enumerates the MSI-X interrupt vectors.
170 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
182 * Address must be 16-byte aligned.
183 * Bits <63:49> are ignored by hardware; software should use a
184 * sign-extended bit <48> for forward compatibility.
[all …]
/Linux-v6.1/drivers/infiniband/hw/irdma/
Duda_d.h1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
9 #define IRDMA_E_UDA_SQ_L4T_SCTP 2
15 #define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM 2
30 #define IRDMA_UDA_QPSQ_MACLEN_LINE 2
32 #define IRDMA_UDA_QPSQ_IPLEN_LINE 2
34 #define IRDMA_UDA_QPSQ_L4T_LINE 2
36 #define IRDMA_UDA_QPSQ_IIPT_LINE 2
69 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48)
76 #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2)
[all …]

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