/Linux-v6.6/arch/arm/include/asm/hardware/ |
D | cp14.h | 35 * Available only in DBGv7.1 45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0) 46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0) 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) 48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0) 49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0) 51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0) 52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0) 53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2) [all …]
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/Linux-v6.6/tools/testing/selftests/hid/tests/ |
D | test_multitouch.py | 24 return 1 << x 29 "SLOT_IS_CONTACTID": BIT(1), 109 input_info=(BusType.USB, 1, 2), argument 130 self.max_contacts = 1 155 self.scantime += 1 179 return (1, []) 187 return (1, []) 190 return (1, []) 198 return 1 206 return 1 [all …]
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D | test_tablet.py | 374 input_info=(BusType.USB, 1, 2), argument 400 return (1, []) 408 return (1, []) 410 return (1, []) 414 return 1 422 return 1 424 return 1 448 events = events[idx + 1 :] 477 p.x += 1 478 p.y -= 1 [all …]
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/Linux-v6.6/arch/arm/mm/ |
D | proc-v7.S | 34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 37 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 85 ALT_UP_B(1f) 87 1: dcache_line_size r2, r3 88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID [all …]
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D | proc-v6.S | 22 #define TTB_C (1 << 0) 23 #define TTB_S (1 << 1) 24 #define TTB_IMP (1 << 2) 26 #define TTB_RGN_WBWA (1 << 3) 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
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D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0 40 mcr p15, 0, r0, c1, c0, 0 @ disable caches 51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 71 mcr p15, 0, r0, c6, c0 @ set area 0, default 76 1: add r4, r4, #1 @ area size *= 2 77 movs r3, r3, lsr #1 78 bne 1b @ count not zero r-shift [all …]
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D | proc-xsc3.S | 56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 70 bcc 1b 72 bpl 1b 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 136 mov r0, #1 [all …]
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D | proc-sa1100.S | 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 93 * 1 = fast idle 127 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 130 bhi 1b 147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer [all …]
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D | cache-v7.S | 43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR 45 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR 50 mov r2, #1 51 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] 52 movs r1, r2, lsl r1 @ #1 shifted left by same amount 53 moveq r1, #1 @ r1 needs value > 0 even if only 1 way 58 1: movw ip, #0x7fff 64 subs r0, r0, #1 @ Set-- 68 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR 69 b 1b [all …]
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D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 137 1: tst r2, #VM_EXEC 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 141 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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D | proc-xscale.S | 69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 100 bne 1b 116 mrc p15, 0, r1, c1, c0, 1 117 bic r1, r1, #1 118 mcr p15, 0, r1, c1, c0, 1 125 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 128 mcr p15, 0, r0, c1, c0, 0 @ disable caches 147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB [all …]
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D | proc-arm926.S | 50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 90 mrc p15, 0, r1, c1, c0, 0 @ Read control register 92 bic r2, r1, #1 << 12 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate [all …]
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/Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
D | g98.fuc0s | 51 .b32 #cmd_query_get + 0x00000 ~1 154 shl b32 $r5 $r4 1 165 mov $r4 1 173 shl b32 $r15 $r4 1 183 mov $r6 #dma_count - 1 189 sub b32 $r6 1 264 cmpu b32 $r6 1 276 or $r2 1 294 mov $r4 1 353 xor $r3 1 [all …]
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/Linux-v6.6/arch/arm/include/debug/ |
D | icedcc.S | 16 mcr p14, 0, \rd, c0, c5, 0 21 mrc p14, 0, \rx, c0, c1, 0 32 subs \rd, \rd, #1 34 mrc p14, 0, \rx, c0, c1, 0 43 mcr p14, 0, \rd, c8, c0, 0 48 mrc p14, 0, \rx, c14, c0, 0 59 subs \rd, \rd, #1 61 mrc p14, 0, \rx, c14, c0, 0 70 mcr p14, 0, \rd, c1, c0, 0 75 mrc p14, 0, \rx, c0, c0, 0 [all …]
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/Linux-v6.6/arch/arm/kernel/ |
D | hyp-stub.S | 116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 124 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE 125 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE 126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 128 mrc p15, 4, r7, c1, c1, 1 @ HDCR 130 mcr p15, 4, r7, c1, c1, 1 @ HDCR 133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR 134 orr r7, #(1 << 5) @ CP15 barriers enabled 137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR 139 mrc p15, 0, r7, c0, c0, 0 @ MIDR [all …]
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/Linux-v6.6/arch/s390/crypto/ |
D | chacha-s390.S | 21 .long 1,0,0,0 26 .long 0,1,2,3 100 VREPF XB1,K1,1 105 VREPF XD1,K3,1 111 VREPF XC1,K2,1 402 la %r1,1(%r1) 442 #define C0 %v2 macro 508 VAF D1,K3,T1 # K[3]+1 514 VLR C0,K2 545 VAF C0,C0,D0 [all …]
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/Linux-v6.6/arch/arm/boot/compressed/ |
D | head.S | 38 mcr p14, 0, \ch, c0, c5, 0 44 mcr p14, 0, \ch, c8, c0, 0 50 mcr p14, 0, \ch, c1, c0, 0 141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR 142 tst \reg, #(1 << 5) @ CP15BEN bit set? 144 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 162 ldrb \tmp2, [\tmp1, #1] 191 * These 7 nops along with the 1 nop immediately below for 213 W(b) 1f [all …]
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/Linux-v6.6/arch/arm/mach-omap2/ |
D | sleep44xx.S | 47 * 1 - CPUx L1 and logic lost: MPUSS CSWR 88 mrc p15, 0, r0, c1, c0, 0 89 bic r0, r0, #(1 << 2) @ Disable the C bit 90 mcr p15, 0, r0, c1, c0, 0 108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 127 tst r0, #(1 << 18) 128 mrcne p15, 0, r0, c1, c0, 1 129 bicne r0, r0, #(1 << 6) @ Disable SMP bit 130 mcrne p15, 0, r0, c1, c0, 1 [all …]
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/Linux-v6.6/tools/testing/selftests/net/forwarding/ |
D | bridge_igmp.sh | 17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03" 19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00… 29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e" 33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e" 39 simple_if_init $h1 192.0.2.1/24 2001:db8:1::1/64 [all …]
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/Linux-v6.6/arch/arm/mach-sunxi/ |
D | headsmp.S | 25 mrc p15, 0, r1, c0, c0, 0 37 mrc p15, 1, r1, c15, c0, 4 39 mcr p15, 1, r1, c15, c0, 4 42 mrc p15, 1, r1, c15, c0, 0 47 mcr p15, 1, r1, c15, c0, 0 50 mrc p15, 1, r1, c9, c0, 2 53 mcr p15, 1, r1, c9, c0, 2
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/Linux-v6.6/arch/arm/mach-spear/ |
D | hotplug.c | 23 " mcr p15, 0, %1, c7, c5, 0\n" in cpu_enter_lowpower() 28 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 30 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 31 " mrc p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 33 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 43 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 44 " orr %0, %0, %1\n" in cpu_leave_lowpower() 45 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 46 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()
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/Linux-v6.6/tools/testing/selftests/cgroup/ |
D | test_cpuset_prs.sh | 11 echo "$1" 23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}') 30 PROG=$1 32 DELAY_FACTOR=1 34 while [[ "$1" = -* ]] 36 case "$1" in 37 -v) VERBOSE=1 39 [[ $DELAY_FACTOR -eq 1 ]] && 70 rmdir A1/A2/A3 A1/A2 A1 B1 > /dev/null 2>&1 72 rmdir test > /dev/null 2>&1 [all …]
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/Linux-v6.6/arch/arm/mach-versatile/ |
D | hotplug.c | 25 "mcr p15, 0, %1, c7, c5, 0\n" in versatile_immitation_enter_lowpower() 26 " mcr p15, 0, %1, c7, c10, 4\n" in versatile_immitation_enter_lowpower() 30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 47 " orr %0, %0, %1\n" in versatile_immitation_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower() [all …]
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/Linux-v6.6/arch/arm/mach-tegra/ |
D | sleep.h | 33 #define CPU_RESETTABLE_SOON 1 39 #define TEGRA_FLUSH_CACHE_ALL 1 44 add \rn, \rn, #1 53 subne \rd, \rcpu, #1 62 subne \rd, \rcpu, #1 70 mrc p15, 0, \rd, c0, c0, 5 82 mrc p15, 0, \tmp1, c0, c0, 0 90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 91 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW 92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR [all …]
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/Linux-v6.6/Documentation/admin-guide/hw-vuln/ |
D | cross-thread-rsb.rst | 9 transitions out of C0 state, the other sibling thread could use return target 10 predictions from the sibling thread that transitioned out of C0. 15 transitioning out of C0. This could result in a guest-controlled return target 38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT 40 processor core to enter 1T mode, it is required that one of the threads 41 requests to transition out of the C0 state. This can be communicated with the 42 HLT instruction or with an MWAIT instruction that requests non-C0. 43 When the thread re-enters the C0 state, the processor transitions back 44 to 2T mode, assuming the other thread is also still in C0 state. 48 16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon [all …]
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