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/Linux-v5.15/arch/arm64/crypto/
Dsha512-ce-core.S15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
[all …]
Dsha2-ce-core.S32 add t1.4s, v\s0\().4s, \rc\().4s
37 add t0.4s, v\s0\().4s, \rc\().4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
106 add_update 0, v1, 16, 17, 18, 19
107 add_update 1, v2, 17, 18, 19, 16
108 add_update 0, v3, 18, 19, 16, 17
109 add_update 1, v4, 19, 16, 17, 18
111 add_update 0, v5, 16, 17, 18, 19
112 add_update 1, v6, 17, 18, 19, 16
[all …]
/Linux-v5.15/drivers/usb/musb/
Dtusb6010.h36 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
45 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) argument
69 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) argument
75 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) argument
79 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) argument
81 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20) argument
84 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
136 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
154 #define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
188 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18) argument
[all …]
/Linux-v5.15/Documentation/hwmon/
Dadm1026.rst22 * gpio_input: int array (min = 1, max = 17)
25 * gpio_output: int array (min = 1, max = 17)
28 * gpio_inverted: int array (min = 1, max = 17)
31 * gpio_normal: int array (min = 1, max = 17)
44 The ADM1026 implements three (3) temperature sensors, 17 voltage sensors,
65 There are 17 voltage sensors. An alarm is triggered if the voltage has
69 higher voltages directly. 3.3V, 5V, 12V, -12V and battery voltage all have
70 dedicated inputs. There are several inputs scaled to 0-3V full-scale range
72 a 0-2.5V full-scale range. A 2.5V or 1.82V reference voltage is provided
/Linux-v5.15/drivers/video/fbdev/
Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
90 /* Register values for 1024x768, 75Hz mode (17) */
91 /* I'm not sure which mode this is (16 or 17), so I'm defining it as 17,
93 * also 17. Just because MacOS can't do this on Valkyrie doesn't mean we
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
[all …]
/Linux-v5.15/arch/x86/include/asm/
Dperf_event_p4.h40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) argument
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) argument
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32) argument
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) argument
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
86 #define p4_config_unpack_emask(v) \ argument
[all …]
/Linux-v5.15/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/Linux-v5.15/include/linux/
Dinet.h12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
21 * $Id: ip.c,v 0.8.4.8 1992/12/12 19:25:04 bir7 Exp $
[all …]
/Linux-v5.15/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
154 # 24 chars 17 lines
158 # D: 29.500 MHz, H: 29.738 kHz, V: 60.00 Hz
171 # 12 chars 17 lines
[all …]
/Linux-v5.15/sound/soc/mxs/
Dmxs-saif.h20 #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ argument
21 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
30 #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ argument
31 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
34 #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ argument
35 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
44 #define BF_SAIF_CTRL_WORD_LENGTH(v) \ argument
45 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
53 #define BP_SAIF_STAT_RSRVD2 17
55 #define BF_SAIF_STAT_RSRVD2(v) \ argument
[all …]
/Linux-v5.15/drivers/staging/media/hantro/
Dhantro_g1_regs.h18 #define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
35 #define G1_REG_CONFIG_TILED_MODE_MSB BIT(17)
36 #define G1_REG_CONFIG_DEC_OUT_TILED_E BIT(17)
58 #define G1_REG_DEC_CTRL0_SORENSON_E BIT(17)
95 #define G1_REG_DEC_CTRL2_TRANSDCTAB BIT(17)
119 #define G1_REG_DEC_CTRL2_HUFFMAN_E BIT(17)
173 #define G1_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 17)
311 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
312 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
313 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
/Linux-v5.15/include/linux/spi/
Dmxs-spi.h31 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ argument
59 (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
62 #define BF_SSP_TIMING_CLOCK_RATE(v) \ argument
63 (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
77 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
86 #define BF_SSP_CTRL1_WORD_LENGTH(v) \ argument
87 (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
93 #define BF_SSP_CTRL1_SSP_MODE(v) \ argument
94 (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
[all …]
/Linux-v5.15/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-regs.h18 #define BF_GPMI_CTRL0_COMMAND_MODE(v) \ argument
19 (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
37 #define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0 argument
43 #define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \ argument
48 #define BP_GPMI_CTRL0_ADDRESS 17
50 #define BF_GPMI_CTRL0_ADDRESS(v) \ argument
51 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
62 #define BF_GPMI_CTRL0_XFER_COUNT(v) \ argument
63 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
74 #define BF_GPMI_ECCCTRL_ECC_CMD(v) \ argument
[all …]
/Linux-v5.15/sound/soc/sunxi/
Dsun4i-spdif.c29 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */ argument
36 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
38 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4) argument
59 #define SUN4I_SPDIF_FCTL_FTX BIT(17)
61 #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8) argument
63 #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3) argument
66 #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0) argument
73 #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12) argument
75 #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4) argument
78 #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0) argument
[all …]
/Linux-v5.15/drivers/gpu/drm/exynos/
Dregs-scaler.h58 * 3 90 94 98 9c 170 174 178 17c
139 #define SCALER_CFG_BLEND_COLOR_DIVIDE_ALPHA_EN (1 << 17)
156 #define SCALER_INT_EN_ILLEGAL_DST_Y_SPAN (1 << 17)
184 #define SCALER_INT_STATUS_ILLEGAL_DST_Y_SPAN (1 << 17)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
[all …]
/Linux-v5.15/sound/soc/qcom/
Dlpass-lpaif-reg.h11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
39 #define LPAIF_I2SCTL_MODE_QUAD45 17
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ argument
69 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
73 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) argument
74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) argument
75 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) argument
78 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \ argument
[all …]
Dlpass-sc7180.c81 struct lpass_variant *v = drvdata->variant; in sc7180_lpass_alloc_dma_channel() local
87 v->hdmi_rdma_channels); in sc7180_lpass_alloc_dma_channel()
89 if (chan >= v->hdmi_rdma_channels) in sc7180_lpass_alloc_dma_channel()
96 v->rdma_channels); in sc7180_lpass_alloc_dma_channel()
98 if (chan >= v->rdma_channels) in sc7180_lpass_alloc_dma_channel()
102 v->wrdma_channel_start + in sc7180_lpass_alloc_dma_channel()
103 v->wrdma_channels, in sc7180_lpass_alloc_dma_channel()
104 v->wrdma_channel_start); in sc7180_lpass_alloc_dma_channel()
106 if (chan >= v->wrdma_channel_start + v->wrdma_channels) in sc7180_lpass_alloc_dma_channel()
182 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
[all …]
/Linux-v5.15/Documentation/networking/device_drivers/ethernet/neterion/
Dvxge.rst38 i) Single function mode (up to 17 queues)
40 ii) Multi function mode (up to 17 functions)
44 - Single Root mode: v1.0 (up to 17 functions)
45 - Multi-Root mode: v1.0 (up to 17 functions)
52 v) Offloads supported: (Enabled by default)
78 Up to 17 hardware based transmit and receive data channels, with
99 Valid range: 1-17
109 v) addr_learn_en
/Linux-v5.15/drivers/comedi/drivers/
Ddac02.c36 * 0 to 5V 0 21 to 22 24
38 * 0 to 10V 0 20 to 22 24
40 * +/-5V 0 21 to 22 23
41 * 1 15 to 16 17
42 * +/-10V 0 20 to 22 23
43 * 1 14 to 16 17
49 * In on pin 16 17 (4-quadrant)
/Linux-v5.15/drivers/media/radio/
Dradio-tea5777.c64 #define TEA5777_W_DEEM_MASK (1LL << 17)
65 #define TEA5777_W_DEEM_SHIFT 17
123 #define TEA5777_R_LEVEL_MASK (0x0f << 17)
124 #define TEA5777_R_LEVEL_SHIFT 17
255 struct v4l2_capability *v) in vidioc_querycap() argument
259 strscpy(v->driver, tea->v4l2_dev->name, sizeof(v->driver)); in vidioc_querycap()
260 strscpy(v->card, tea->card, sizeof(v->card)); in vidioc_querycap()
261 strlcat(v->card, " TEA5777", sizeof(v->card)); in vidioc_querycap()
262 strscpy(v->bus_info, tea->bus_info, sizeof(v->bus_info)); in vidioc_querycap()
280 struct v4l2_tuner *v) in vidioc_g_tuner() argument
[all …]
/Linux-v5.15/tools/usb/
Dhcd-tests.sh115 do_test -t 14 -c 15000 -s 256 -v 1
118 do_test -t 21 -c 100 -s 256 -v 1
129 do_test -t 3 -v 421
132 echo "test 17: $COUNT transfers, unaligned DMA map by core"
133 do_test -t 17
144 do_test -t 7 -v 579
147 do_test -t 7 -v 41
150 do_test -t 7 -v 63
167 # do_test -t 15 -g 3 -v 0
169 do_test -t 15 -g 8 -v 0
[all …]
/Linux-v5.15/sound/soc/fsl/
Dfsl_esai.h59 #define ESAI_ECR_ERI_SHIFT 17
120 #define ESAI_xFCR_xWA(v) (((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK) argument
124 #define ESAI_xFCR_xFWM(v) ((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK) argument
163 #define ESAI_SAISR_TODFE_SHIFT 17
242 #define ESAI_xCR_PADC_SHIFT 17
300 #define ESAI_xCCR_xFP(v) ((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK) argument
304 #define ESAI_xCCR_xDC(v) ((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK) argument
312 #define ESAI_xCCR_xPM(v) ((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK) argument
318 #define ESAI_xSMA_xS(v) ((v) & ESAI_xSMA_xS_MASK) argument
322 #define ESAI_xSMB_xS(v) (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK) argument
[all …]
/Linux-v5.15/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_regs.h48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16)) argument
49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16)) argument
50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16)) argument
86 #define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)
105 #define GLB_IRQ_STATUS_CU1 BIT(17)
192 #define LPU_STATUS_ACE1 BIT(17)
363 #define SC_CTRL_ASM BIT(17)
412 #define BS_CTRL_SBS BIT(17)
445 #define IPS_CTRL_SBS BIT(17)
466 #define SC_COEFF_G_ADDR BIT(17)

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