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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
Dallwinner,sun7i-a20-gmac-clk.yaml26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
/Linux-v5.15/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/Linux-v5.15/drivers/media/dvb-frontends/
Ddvb-pll.c74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
Dstv0367.c67 u8 bw; /* channel width 6, 7 or 8 in MHz */
286 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"); in stv0367_pll_setup()
296 /* set internal freq to 53.125MHz */ in stv0367_pll_setup()
307 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); in stv0367_pll_setup()
800 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
853 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
1082 /*set IIR filter once for 6,7 or 8MHz BW*/ in stv0367ter_algo()
1446 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); in stv0367ter_snr_readreg()
1686 .frequency_min_hz = 47 * MHz,
1687 .frequency_max_hz = 862 * MHz,
[all …]
/Linux-v5.15/drivers/media/pci/cx18/
Dcx18-firmware.c223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
/Linux-v5.15/drivers/clk/spear/
Dspear1340_clock.c168 /* PCLK 24MHz */
169 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
170 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
171 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
172 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
173 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
174 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
181 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
182 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml52 - description: Master/Core clock, has to be >= 125 MHz
53 for SS operation and >= 60MHz for HS operation.
56 in host mode. Its frequency should be 19.2MHz.
75 - description: Must be 19.2MHz (19200000).
76 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
Ddwc3-xilinx.txt8 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
/Linux-v5.15/drivers/media/firewire/
Dfiredtv-fe.c173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
/Linux-v5.15/Documentation/devicetree/bindings/net/dsa/
Dmicrochip,ksz.yaml40 microchip,synclko-125:
43 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c45 *| MII | n/a | 25Mhz |
48 *| GMII | 125Mhz | 25Mhz |
49 *| | clk-125/txclk | txclk |
51 *| RGMII | 125Mhz | 25Mhz |
52 *| | clk-125/txclk | clkgen |
55 *| RMII | n/a | 25Mhz |
Ddwmac-meson8b.c36 * cycle of the 125MHz RGMII TX clock):
357 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
359 * a register) based on the line-speed (125MHz for Gbit speeds, in meson8b_init_prg_eth()
360 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). in meson8b_init_prg_eth()
362 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); in meson8b_init_prg_eth()
/Linux-v5.15/drivers/clk/sunxi/
Dclk-a20-gmac.c25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
/Linux-v5.15/drivers/net/wireless/intel/iwlwifi/mvm/
Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
17 /* frequency 3733MHz */
21 /* frequency 4267MHz */
28 /* frequency 4000MHz */
33 /* frequency 4400MHz */
34 {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
40 /* frequency 5200MHz */
44 /* frequency 6000MHz */
49 /* frequency 6400MHz */
/Linux-v5.15/drivers/clk/uniphier/
Dclk-uniphier-sys.c83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/Linux-v5.15/drivers/clk/mvebu/
Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
/Linux-v5.15/drivers/i2c/busses/
Di2c-stm32f4.c120 * @parent_rate: I2C clock parent rate in MHz
162 * a minimum value of 2 MHz and a maximum value of 46 MHz due in stm32f4_i2c_set_periph_clk_freq()
174 * frequency should be between a minimum value of 6 MHz and a in stm32f4_i2c_set_periph_clk_freq()
175 * maximum value of 46 MHz due to hardware limitation in stm32f4_i2c_set_periph_clk_freq()
202 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
203 * programmed with 0x9. (1000 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
208 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
209 * programmed with 0x3. (300 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
213 * is not higher than 46 MHz . As a result trise is at most 4 bits wide in stm32f4_i2c_set_rise_time()
237 * For example with parent rate = 2 MHz: in stm32f4_i2c_set_speed_mode()
[all …]
/Linux-v5.15/drivers/net/phy/
Dmotorcomm.c23 * 2b11 125m from pll
87 /* set clock mode to 125mhz */ in yt8511_config_init()
/Linux-v5.15/arch/arm/mach-omap2/
Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
85 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
97 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
112 den = 125; in realtime_counter_init()
136 /* Program it for 38.4 MHz */ in realtime_counter_init()
/Linux-v5.15/Documentation/devicetree/bindings/net/
Drockchip-dwmac.yaml73 For RGMII, it must be "input", means main clock(125MHz)
75 For RMII, "input" means PHY provides the reference clock(50MHz),
/Linux-v5.15/sound/soc/codecs/
Dtlv320aic23.c193 * 11.2896 Mhz /128 = *88.2k /192 = 58.8k
194 * 12.0000 Mhz /125 = *96k /136 = 88.235K
195 * 12.2880 Mhz /128 = *96k /192 = 64k
196 * 16.9344 Mhz /128 = 132.3k /192 = *88.2k
197 * 18.4320 Mhz /128 = 144k /192 = *96k
202 * USB BOSR 0-250/2 = 125, 1-272/2 = 136
205 128, 125, 192, 136
/Linux-v5.15/drivers/net/dsa/sja1105/
Dsja1105_clocking.c130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
357 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
480 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
481 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
482 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
483 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
603 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
606 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
609 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ in sja1105_rgmii_clocking_setup()
700 /* PLL1 must be enabled and output 50 Mhz. in sja1105_cgu_rmii_pll_config()
[all …]
/Linux-v5.15/drivers/pwm/
Dpwm-ntxec.c46 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
49 #define TIME_BASE_NS 125
/Linux-v5.15/Documentation/devicetree/bindings/devfreq/
Drk3399_dmc.txt64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
70 MHz (Mega Hz). When DDR frequency is less than
75 the ODT disable frequency in MHz (Mega Hz).
101 then ODT disable frequency in MHz (Mega Hz).
128 MHz (Mega Hz). When the DDR frequency is less then
190 rockchip,phy_dll_dis_freq = <125>;

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