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/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml40 # (one for the internal 100base-T1 PHYs and the other for the single
41 # 100base-TX PHY). The "reg" property does not have physical significance.
42 # The PHY addresses to port correspondence is as follows: for 100base-T1,
43 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
92 rx-internal-delay-ps:
93 $ref: "#/$defs/internal-delay-ps"
94 tx-internal-delay-ps:
95 $ref: "#/$defs/internal-delay-ps"
102 internal-delay-ps:
104 Disable tunable delay lines using 0 ps, or enable them and select
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
32 600 -480ps 0011
33 800 -360ps 0100
34 1000 -240ps 0101
35 1200 -120ps 0110
36 1400 0ps 0111
[all …]
Dti,dp83869.yaml18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
67 rx-internal-delay-ps:
73 tx-internal-delay-ps:
97 rx-internal-delay-ps = <2000>;
98 tx-internal-delay-ps = <2000>;
Dti,dp83822.yaml14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
49 100base-fx (full and half duplex) modes.
51 rx-internal-delay-ps:
58 tx-internal-delay-ps:
77 rx-internal-delay-ps = <1>;
78 tx-internal-delay-ps = <1>;
Dallwinner,sun8i-a83t-emac.yaml76 allwinner,tx-delay-ps:
80 multipleOf: 100
82 External RGMII PHY TX clock delay chain value in ps.
84 allwinner,rx-delay-ps:
88 multipleOf: 100
90 External RGMII PHY TX clock delay chain value in ps.
101 allwinner,rx-delay-ps:
105 multipleOf: 100
107 External RGMII PHY TX clock delay chain value in ps.
/Linux-v6.1/arch/parisc/kernel/
Dhardware.c48 {HPHW_NPROC,0x182,0x4,0x91,"TNT 100 (891,T500)"},
78 {HPHW_NPROC,0x317,0x4,0x81,"Scorpio 100 (715/100)"},
81 {HPHW_NPROC,0x320,0x4,0x81,"Spectra (725/100)"},
89 {HPHW_NPROC,0x484,0x4,0x81,"UL Proc L-100 (811/D210,D310)"},
113 {HPHW_NPROC,0x580,0x4,0x81,"KittyHawk DC2-100 (K100)"},
115 {HPHW_NPROC,0x582,0x4,0x91,"KittyHawk DC3 100 (K400)"},
118 {HPHW_NPROC,0x585,0x4,0x91,"SkyHawk 100"},
122 {HPHW_NPROC,0x589,0x4,0x81,"UL Proc 1-way T'100 (821/D250,D350)"},
123 {HPHW_NPROC,0x58A,0x4,0x91,"UL Proc 2-way T'100 (831/D250,D350)"},
124 {HPHW_NPROC,0x58B,0x4,0x91,"KittyHawk DC2 100 (K200)"},
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mp-dhcom-pdk2.dts7 * DHCOM PCB number: 660-100 or newer
129 max-speed = <100>;
134 rxc-skew-ps = <3000>;
135 rxd0-skew-ps = <0>;
136 rxd1-skew-ps = <0>;
137 rxd2-skew-ps = <0>;
138 rxd3-skew-ps = <0>;
139 rxdv-skew-ps = <0>;
140 txc-skew-ps = <3000>;
141 txd0-skew-ps = <0>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx6q-mba6.dtsi16 rxdv-skew-ps = <180>;
17 txen-skew-ps = <120>;
18 rxd3-skew-ps = <180>;
19 rxd2-skew-ps = <180>;
20 rxd1-skew-ps = <180>;
21 rxd0-skew-ps = <180>;
22 txd3-skew-ps = <120>;
23 txd2-skew-ps = <0>;
24 txd1-skew-ps = <180>;
25 txd0-skew-ps = <360>;
[all …]
Dsocfpga_arria10_socdk.dtsi74 * These skews assume the user's FPGA design is adding 600ps of delay
81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
[all …]
Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <2600>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <2000>;
93 * because the LCD module does not work at the standard 100Khz
Dsocfpga_cyclone5_socdk.dts69 rxd0-skew-ps = <0>;
70 rxd1-skew-ps = <0>;
71 rxd2-skew-ps = <0>;
72 rxd3-skew-ps = <0>;
73 txen-skew-ps = <0>;
74 txc-skew-ps = <2600>;
75 rxdv-skew-ps = <0>;
76 rxc-skew-ps = <2000>;
97 * because the LCD module does not work at the standard 100Khz
/Linux-v6.1/drivers/gpu/drm/radeon/
Dsumo_dpm.c76 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps() local
78 return ps; in sumo_get_ps()
135 u32 grs = 256 * 25 / 100; in sumo_program_grsd()
320 pi->pasi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
321 pi->asi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
345 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_bsp() local
347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
349 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
354 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
359 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
[all …]
Dtrinity_dpm.c40 #define TRINITY_MGCG_SEQUENCE 100
123 #define TRINITY_SYSLS_SEQUENCE 100
306 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps() local
308 return ps; in trinity_get_ps()
828 struct trinity_ps *ps = trinity_get_ps(rps); in trinity_setup_uvd_clock_table() local
829 u32 uvdstates = (ps->vclk_low_divider | in trinity_setup_uvd_clock_table()
830 ps->vclk_high_divider << 8 | in trinity_setup_uvd_clock_table()
831 ps->dclk_low_divider << 16 | in trinity_setup_uvd_clock_table()
832 ps->dclk_high_divider << 24); in trinity_setup_uvd_clock_table()
1162 struct trinity_ps *ps = trinity_get_ps(rps); in trinity_dpm_force_performance_level() local
[all …]
Dsi_dpm.c266 100,
302 100,
320 100,
499 100,
507 100
548 100,
566 100,
584 100,
999 100
1526 100
[all …]
Dni_dpm.c651 #define NISLANDS_SYSLS_SEQUENCE 100
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps() local
737 return ps; in ni_get_ps()
788 struct ni_ps *ps = ni_get_ps(rps); in ni_apply_state_adjust_rules() local
807 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
[all …]
Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps() local
39 return ps; in rs780_get_ps()
420 udelay(100); in rs780_force_fbdiv()
529 udelay(100); in rs780_enable_voltage_scaling()
751 struct igp_ps *ps = rs780_get_ps(rps); in rs780_parse_pplib_clock_info() local
756 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()
759 ps->sclk_high = sclk; in rs780_parse_pplib_clock_info()
763 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN; in rs780_parse_pplib_clock_info()
764 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN; in rs780_parse_pplib_clock_info()
767 ps->min_voltage = RS780_VDDC_LEVEL_LOW; in rs780_parse_pplib_clock_info()
[all …]
/Linux-v6.1/tools/testing/selftests/vm/
Dthuge-gen.c95 void show(unsigned long ps) in show() argument
97 char buf[100]; in show()
98 if (ps == getpagesize()) in show()
100 printf("%luMB: ", ps >> 20); in show()
104 ps >> 10); in show()
112 char buf[100]; in read_sysfs()
135 unsigned long read_free(unsigned long ps) in read_free() argument
137 return read_sysfs(ps != getpagesize(), in read_free()
139 ps >> 10); in read_free()
236 unsigned long ps = page_sizes[i]; in main() local
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { in smu10_set_soft_max_gfxclk_by_freq()
265 smu10_data->gfx_max_freq_limit = clock * 100; in smu10_set_soft_max_gfxclk_by_freq()
470 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; in smu10_get_clock_voltage_dependency_table()
577 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100; in smu10_hwmgr_backend_init()
578 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100; in smu10_hwmgr_backend_init()
619 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
632 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
649 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
666 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
[all …]
Dsmu7_hwmgr.c89 {1, 0, 100, 30, 1, 0, 100, 10},
92 {1, 0, 11, 50, 1, 0, 100, 10},
1787 data->current_profile_setting.sclk_down_hyst = 100; in smu7_init_dpm_defaults()
1806 data->current_profile_setting.mclk_down_hyst = 100; in smu7_init_dpm_defaults()
1823 data->fast_watermark_threshold = 100; in smu7_init_dpm_defaults()
2530 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; in smu7_thermal_parameter_init()
3128 …percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1]… in smu7_get_profiling_clk()
3140 tmp_sclk = tmp_mclk * percentage / 100; in smu7_get_profiling_clk()
3318 stable_pstate_sclk = (max_limits->sclk * 75) / 100; in smu7_apply_state_adjust_rules()
3445 struct pp_power_state *ps; in smu7_dpm_get_mclk() local
[all …]
/Linux-v6.1/drivers/net/wireless/ath/
Ddfs_pattern_detector.c38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100)
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
44 #define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100)
93 FCC_PATTERN(5, 50, 100, 1000, 2000, 1, 1, true),
118 JP_PATTERN(7, 50, 100, 1000, 2000, 1, 3, 50, true),
298 struct pri_sequence *ps = pd->add_pulse(pd, event); in dpd_add_pulse() local
299 if (ps != NULL) { in dpd_add_pulse()
306 ps->pri, ps->count, ps->count_falses); in dpd_add_pulse()
/Linux-v6.1/include/linux/phy/
Dphy-mipi-dphy.h22 * Maximum value: 60000 ps
34 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
56 * Minimum value: 38000 ps
57 * Maximum value: 95000 ps
68 * Minimum value: 95000 ps
69 * Maximum value: 300000 ps
79 * Maximum value: 38000 ps
90 * Minimum value: 60000 ps
108 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
119 * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
[all …]
/Linux-v6.1/arch/microblaze/boot/dts/
Dsystem.dts137 xlnx,mch-plb-clk-period-ps = <0x1f40>;
166 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
167 xlnx,tavdv-ps-mem-1 = <0x3a98>;
168 xlnx,tavdv-ps-mem-2 = <0x3a98>;
169 xlnx,tavdv-ps-mem-3 = <0x3a98>;
170 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
171 xlnx,tcedv-ps-mem-1 = <0x3a98>;
172 xlnx,tcedv-ps-mem-2 = <0x3a98>;
173 xlnx,tcedv-ps-mem-3 = <0x3a98>;
174 xlnx,thzce-ps-mem-0 = <0x88b8>;
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw88/
Dps.c8 #include "ps.h"
97 100, 15000, true, rtwdev, in rtw_power_mode_change()
128 * PS bit could be sent due to incorrect REG_TCR setting. in __rtw_fw_leave_lps_check_reg()
130 * In our test, 100ms should be enough for firmware to finish in __rtw_fw_leave_lps_check_reg()
131 * the flow. If REG_TCR Register is still incorrect after 100ms, in __rtw_fw_leave_lps_check_reg()
219 "Should enter LPS before entering deep PS\n"); in __rtw_enter_lps_deep()
265 "Should leave deep PS before leaving LPS\n"); in __rtw_leave_lps()
/Linux-v6.1/drivers/soc/apple/
Dapple-pmgr-pwrstate.c37 #define APPLE_PMGR_PS_SET_TIMEOUT 100
55 struct apple_pmgr_ps *ps = genpd_to_apple_pmgr_ps(genpd); in apple_pmgr_ps_set() local
58 ret = regmap_read(ps->regmap, ps->offset, &reg); in apple_pmgr_ps_set()
64 dev_err(ps->dev, "PS %s: powering off with RESET active\n", in apple_pmgr_ps_set()
70 dev_dbg(ps->dev, "PS %s: pwrstate = 0x%x: 0x%x\n", genpd->name, pstate, reg); in apple_pmgr_ps_set()
72 regmap_write(ps->regmap, ps->offset, reg); in apple_pmgr_ps_set()
75 ps->regmap, ps->offset, reg, in apple_pmgr_ps_set()
79 dev_err(ps->dev, "PS %s: Failed to reach power state 0x%x (now: 0x%x)\n", in apple_pmgr_ps_set()
86 regmap_write(ps->regmap, ps->offset, reg); in apple_pmgr_ps_set()
92 static bool apple_pmgr_ps_is_active(struct apple_pmgr_ps *ps) in apple_pmgr_ps_is_active() argument
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/pm/legacy-dpm/
Dsi_dpm.c369 100,
405 100,
423 100,
602 100,
610 100
651 100,
669 100,
687 100,
1102 100
1629 100
[all …]

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