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/Linux-v5.4/drivers/video/logo/
Dlogo_linux_mono.pbm4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1
13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[all …]
Dlogo_superh_mono.pbm4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1
13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[all …]
/Linux-v5.4/arch/mips/include/asm/octeon/
Dcvmx-fpa-defs.h36 #define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
45 …ine CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
46 …fine CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
54 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
91 uint64_t frd:1;
92 uint64_t fpf0:1;
93 uint64_t fpf1:1;
94 uint64_t ffr:1;
95 uint64_t fdr:1;
97 uint64_t fdr:1;
[all …]
Dcvmx-npi-defs.h32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
183 uint64_t csr_bs:1;
[all …]
Dcvmx-npei-defs.h146 uint32_t ca:1;
148 uint32_t addr_v:1;
150 uint32_t addr_v:1;
152 uint32_t ca:1;
163 uint64_t pkt_rdf:1;
165 uint64_t pcr_gim:1;
166 uint64_t pkt_pif:1;
167 uint64_t pcsr_int:1;
168 uint64_t pcsr_im:1;
169 uint64_t pcsr_cnt:1;
[all …]
Dcvmx-pci-defs.h67 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
68 #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
70 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
71 #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
73 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
74 #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
76 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
86 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
91 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
96 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
[all …]
Dcvmx-gmxx-defs.h159 …) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 204…
160 …) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 204…
195 …) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 204…
237 …) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 204…
329 #define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) *…
330 #define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) *…
331 #define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1…
348 uint64_t hg2tx_en:1;
349 uint64_t hg2rx_en:1;
350 uint64_t phys_en:1;
[all …]
Dcvmx-pemx-defs.h31 …) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * …
33 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x…
34 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) …
35 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1)…
36 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1…
37 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1…
38 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1…
39 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) *…
40 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0…
[all …]
Dcvmx-pescx-defs.h31 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1)…
32 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1…
33 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x…
34 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x…
35 …_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) …
37 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1)…
38 #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * …
39 #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1)…
40 #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1)…
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_4_1_offset.h29 …ne mmDAGB0_RDCLI0_BASE_IDX 1
31 …ne mmDAGB0_RDCLI1_BASE_IDX 1
33 …ne mmDAGB0_RDCLI2_BASE_IDX 1
35 …ne mmDAGB0_RDCLI3_BASE_IDX 1
37 …ne mmDAGB0_RDCLI4_BASE_IDX 1
39 …ne mmDAGB0_RDCLI5_BASE_IDX 1
41 …ne mmDAGB0_RDCLI6_BASE_IDX 1
43 …ne mmDAGB0_RDCLI7_BASE_IDX 1
45 …ne mmDAGB0_RDCLI8_BASE_IDX 1
47 …ne mmDAGB0_RDCLI9_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dml/
Ddc_features.h29 #define DC__PRESENT 1
30 #define DC__PRESENT__1 1
33 #define DC__NUM_DPP__4 1
34 #define DC__NUM_DPP__0_PRESENT 1
35 #define DC__NUM_DPP__1_PRESENT 1
36 #define DC__NUM_DPP__2_PRESENT 1
37 #define DC__NUM_DPP__3_PRESENT 1
39 #define DC__NUM_DPP__MAX__8 1
41 #define DC__PIPE_10BIT__0 1
42 #define DC__PIPE_10BIT__MAX 1
[all …]
/Linux-v5.4/drivers/pinctrl/mvebu/
Dpinctrl-kirkwood.c20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
36 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
37 MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1, 1)),
[all …]
/Linux-v5.4/include/uapi/linux/
Dmap_to_7segment.h67 #define BIT_SEG7_B 1
106 _SEG7('!',0,0,0,0,1,1,0), _SEG7('"',0,1,0,0,0,1,0), _SEG7('#',0,1,1,0,1,1,0),\
107 _SEG7('$',1,0,1,1,0,1,1), _SEG7('%',0,0,1,0,0,1,0), _SEG7('&',1,0,1,1,1,1,1),\
108 _SEG7('\'',0,0,0,0,0,1,0),_SEG7('(',1,0,0,1,1,1,0), _SEG7(')',1,1,1,1,0,0,0),\
109 _SEG7('*',0,1,1,0,1,1,1), _SEG7('+',0,1,1,0,0,0,1), _SEG7(',',0,0,0,0,1,0,0),\
110 _SEG7('-',0,0,0,0,0,0,1), _SEG7('.',0,0,0,0,1,0,0), _SEG7('/',0,1,0,0,1,0,1),
113 _SEG7('0',1,1,1,1,1,1,0), _SEG7('1',0,1,1,0,0,0,0), _SEG7('2',1,1,0,1,1,0,1),\
114 _SEG7('3',1,1,1,1,0,0,1), _SEG7('4',0,1,1,0,0,1,1), _SEG7('5',1,0,1,1,0,1,1),\
115 _SEG7('6',1,0,1,1,1,1,1), _SEG7('7',1,1,1,0,0,0,0), _SEG7('8',1,1,1,1,1,1,1),\
116 _SEG7('9',1,1,1,1,0,1,1),
[all …]
/Linux-v5.4/arch/arm/mach-orion5x/
Dmpp.h16 #define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
17 #define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
18 #define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
20 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
21 #define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
22 #define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
23 #define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
25 #define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
26 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
27 #define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma2/
Dsdma2_4_2_2_offset.h29 …ne mmSDMA2_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA2_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA2_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA2_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA2_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA2_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA2_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA2_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA2_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma3/
Dsdma3_4_2_2_offset.h29 …ne mmSDMA3_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA3_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA3_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA3_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA3_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA3_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA3_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma4/
Dsdma4_4_2_2_offset.h29 …ne mmSDMA4_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA4_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA4_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA4_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA4_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA4_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA4_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA4_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA4_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA4_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma5/
Dsdma5_4_2_2_offset.h29 …ne mmSDMA5_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA5_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA5_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA5_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA5_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA5_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA5_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma6/
Dsdma6_4_2_2_offset.h29 …ne mmSDMA6_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA6_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA6_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA6_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA6_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA6_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA6_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA6_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA6_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma7/
Dsdma7_4_2_2_offset.h29 …ne mmSDMA7_UCODE_ADDR_BASE_IDX 1
31 …ne mmSDMA7_UCODE_DATA_BASE_IDX 1
33 …ne mmSDMA7_VM_CNTL_BASE_IDX 1
35 …ne mmSDMA7_VM_CTX_LO_BASE_IDX 1
37 …ne mmSDMA7_VM_CTX_HI_BASE_IDX 1
39 …ne mmSDMA7_ACTIVE_FCN_ID_BASE_IDX 1
41 …ne mmSDMA7_VM_CTX_CNTL_BASE_IDX 1
43 …ne mmSDMA7_VIRT_RESET_REQ_BASE_IDX 1
45 …ne mmSDMA7_VF_ENABLE_BASE_IDX 1
47 …ne mmSDMA7_CONTEXT_REG_TYPE0_BASE_IDX 1
[all …]
/Linux-v5.4/fs/cifs/
Dcifs_uniupr.h29 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 100-10f */
30 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 110-11f */
31 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 120-12f */
32 0, 0, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, 0, /* 130-13f */
33 -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, /* 140-14f */
34 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 150-15f */
35 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 160-16f */
36 0, -1, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, 0, /* 170-17f */
37 0, 0, 0, -1, 0, -1, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, /* 180-18f */
38 0, 0, -1, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, /* 190-19f */
[all …]
/Linux-v5.4/drivers/staging/octeon/
Docteon-stubs.h20 #define CVMX_FPA_WQE_POOL (1)
29 #define CVMX_PIP_NUM_INPUT_PORTS 1
46 uint64_t vlan_valid:1;
47 uint64_t vlan_stacked:1;
48 uint64_t unassigned:1;
49 uint64_t vlan_cfi:1;
53 uint64_t dec_ipcomp:1;
54 uint64_t tcp_or_udp:1;
55 uint64_t dec_ipsec:1;
56 uint64_t is_v6:1;
[all …]
/Linux-v5.4/fs/jfs/
Djfs_uniupr.c29 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 100-10f */
30 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 110-11f */
31 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 120-12f */
32 0, 0, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, 0, /* 130-13f */
33 -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, /* 140-14f */
34 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 150-15f */
35 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, /* 160-16f */
36 0, -1, 0, -1, 0, -1, 0, -1, 0, 0, -1, 0, -1, 0, -1, 0, /* 170-17f */
37 0, 0, 0, -1, 0, -1, 0, 0, -1, 0, 0, 0, -1, 0, 0, 0, /* 180-18f */
38 0, 0, -1, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, /* 190-19f */
[all …]
/Linux-v5.4/arch/x86/kernel/
Duprobes.c42 #define OPCODE2(insn) ((insn)->opcode.bytes[1])
71 * 07,17,1f - pop es/ss/ds
76 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
87 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
89 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
90 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
91 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
92 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
93 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
94 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
[all …]
/Linux-v5.4/arch/arm/mach-mv78xx0/
Dmpp.h24 #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
26 #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
27 #define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
28 #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
29 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
31 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
32 #define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
33 #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
34 #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
36 #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
[all …]

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