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/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dchang84.c39 *pevent = &chan->fifo->uevent; in g84_fifo_chan_ntfy()
44 return -EINVAL; in g84_fifo_chan_ntfy()
50 switch (engine->subdev.type) { in g84_fifo_chan_engine_addr()
52 case NVKM_ENGINE_SW : return -1; in g84_fifo_chan_engine_addr()
64 WARN_ON(1); in g84_fifo_chan_engine_addr()
65 return -1; in g84_fifo_chan_engine_addr()
74 struct nv50_fifo *fifo = chan->fifo; in g84_fifo_chan_engine_fini()
75 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in g84_fifo_chan_engine_fini()
76 struct nvkm_device *device = subdev->device; in g84_fifo_chan_engine_fini()
85 engn = fifo->base.func->engine_id(&fifo->base, engine) - 1; in g84_fifo_chan_engine_fini()
[all …]
Dchannv50.c34 switch (engine->subdev.type) { in nv50_fifo_chan_engine_addr()
36 case NVKM_ENGINE_SW : return -1; in nv50_fifo_chan_engine_addr()
40 WARN_ON(1); in nv50_fifo_chan_engine_addr()
41 return -1; in nv50_fifo_chan_engine_addr()
48 int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); in nv50_fifo_chan_engine()
50 return &chan->engn[engi]; in nv50_fifo_chan_engine()
59 struct nv50_fifo *fifo = chan->fifo; in nv50_fifo_chan_engine_fini()
60 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in nv50_fifo_chan_engine_fini()
61 struct nvkm_device *device = subdev->device; in nv50_fifo_chan_engine_fini()
84 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in nv50_fifo_chan_engine_fini()
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Dchannv50.h1 /* SPDX-License-Identifier: MIT */
14 struct nvkm_gpuobj *eng; member
19 #define NV50_FIFO_ENGN_GR 1
24 #define G84_FIFO_ENGN_GR 1
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c43 struct gk104_clk_info eng[16]; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
99 P = 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
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Dgf100.c43 struct gf100_clk_info eng[16]; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
76 P = 1; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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Dgt215.c36 struct gt215_clk_info eng[nv_clk_src_max]; member
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
122 /* no post-divider on these.. in read_pll()
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/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Dgmc_v11_0.c86 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v11_0_process_interrupt()
90 addr = (u64)entry->src_data[0] << 12; in gmc_v11_0_process_interrupt()
91 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v11_0_process_interrupt()
99 if (entry->vmid_src == AMDGPU_GFXHUB_0) in gmc_v11_0_process_interrupt()
100 RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
102 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
103 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); in gmc_v11_0_process_interrupt()
110 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v11_0_process_interrupt()
112 dev_err(adev->dev, in gmc_v11_0_process_interrupt()
115 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v11_0_process_interrupt()
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Dgmc_v10_0.c100 bool retry_fault = !!(entry->src_data[1] & 0x80); in gmc_v10_0_process_interrupt()
101 bool write_fault = !!(entry->src_data[1] & 0x20); in gmc_v10_0_process_interrupt()
102 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
107 addr = (u64)entry->src_data[0] << 12; in gmc_v10_0_process_interrupt()
108 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v10_0_process_interrupt()
111 /* Returning 1 here also prevents sending the IV to the KFD */ in gmc_v10_0_process_interrupt()
114 if (entry->ih != &adev->irq.ih_soft && in gmc_v10_0_process_interrupt()
115 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, in gmc_v10_0_process_interrupt()
116 entry->timestamp)) in gmc_v10_0_process_interrupt()
117 return 1; in gmc_v10_0_process_interrupt()
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Dgmc_v9_0.c99 [1][0] = "MP0",
108 [0][1] = "MP1",
109 [1][1] = "MP0",
110 [2][1] = "VCN",
111 [3][1] = "VCNU",
112 [4][1] = "HDP",
113 [5][1] = "XDP",
114 [6][1] = "DBGU0",
115 [7][1] = "DCE",
116 [8][1] = "DCEDWB0",
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/Linux-v6.1/drivers/mtd/nand/
Decc-mxic.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
33 #define SDMA_MAIN BIT(1)
68 #define READ_NAND BIT(1)
114 static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in ext_ecc_eng_to_mxic() argument
116 return container_of(eng, struct mxic_ecc_engine, external_engine); in ext_ecc_eng_to_mxic()
119 static struct mxic_ecc_engine *pip_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in pip_ecc_eng_to_mxic() argument
121 return container_of(eng, struct mxic_ecc_engine, pipelined_engine); in pip_ecc_eng_to_mxic()
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic() local
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/Linux-v6.1/include/linux/
Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
[all …]
/Linux-v6.1/drivers/spi/
Dspi-mxic.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mtd/nand-ecc-mxic.h>
20 #include <linux/spi/spi-mem.h>
29 #define HC_CFG_TYPE_SPI_NAND 1
40 #define HC_CFG_MAN_CS_EN BIT(1)
58 #define INT_TX_NOT_FULL BIT(1)
74 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
86 #define OP_BUSW_2 1
92 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
117 #define DMAC_CFG_QE(x) (((x) + 1) << 16)
[all …]
/Linux-v6.1/drivers/cpufreq/
Dsti-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
24 #define HW_INFO_INDEX 1
25 #define MAJOR_ID_INDEX 1
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
77 return ((socid >> VERSION_SHIFT) & 0xf) + 1; in sti_cpufreq_fetch_major()
83 struct device_node *np = dev->of_node; in sti_cpufreq_fetch_minor()
88 ret = of_property_read_u32_index(np, "st,syscfg-eng", in sti_cpufreq_fetch_minor()
154 struct device_node *np = dev->of_node; in sti_cpufreq_set_opp_info()
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/Linux-v6.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
26 * NOTE: For engine-registers, GuC only needs the register offsets
27 * from the engine-mmio-base
73 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \
74 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \
92 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \
96 /* XE_LPD - Global */
103 /* XE_LPD - Render / Compute Per-Class */
110 /* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
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/Linux-v6.1/drivers/infiniband/hw/hfi1/
Dsdma.h1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
3 * Copyright(c) 2015 - 2018 Intel Corporation.
22 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
25 #define SDMA_MAP_SINGLE 1
48 #define SDMA_AHG_COPY 1
61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
[all …]
/Linux-v6.1/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
118 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
155 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/iio/accel/
Dmemsensing,msa311.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: MEMSensing digital 3-Axis accelerometer
11 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
14 MSA311 is a tri-axial, low-g accelerometer with I2C digital output for
16 scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements
17 with output data rates from 1Hz to 1000Hz.
19 https://cdn-shop.adafruit.com/product-files/5309/MSA311-V1.1-ENG.pdf
26 maxItems: 1
[all …]
/Linux-v6.1/drivers/soc/tegra/fuse/
Dspeedo-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
53 int sku = sku_info->sku_id; in rev_sku_to_speedo_ids()
56 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids()
57 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
58 sku_info->gpu_speedo_id = 0; in rev_sku_to_speedo_ids()
62 case 0x00: /* Eng sku */ in rev_sku_to_speedo_ids()
68 sku_info->cpu_speedo_id = 2; in rev_sku_to_speedo_ids()
74 sku_info->cpu_speedo_id = 2; in rev_sku_to_speedo_ids()
75 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
[all …]
/Linux-v6.1/arch/sparc/include/uapi/asm/
Denvctrl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
8 * Copyright (C) 2000 Vinh Truong (vinh.truong@eng.sun.com)
9 * VT - Add all ioctl commands and environment status definitions
10 * VT - Add application note
13 #define _SPARC64_ENVCTRL_H 1
79 * if (read(fd, rslt, 1) <= 0) {
/Linux-v6.1/Documentation/fb/
Dsh7760fb.rst6 -----------
8 supports (in theory) resolutions ranging from 1x1 to 1024x1024,
9 with color depths ranging from 1 to 16 bits, on STN, DSTN and TFT Panels.
29 - drivers/video/sh7760fb.c
30 - include/asm-sh/sh7760fb.h
31 - Documentation/fb/sh7760fb.rst
33 1. Platform setup
34 -----------------
47 --------------------
53 (http://documentation.renesas.com/eng/products/mpumcu/e602291_sh7760.pdf)
[all …]
/Linux-v6.1/include/uapi/linux/spi/
Dspidev.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
6 * Andrea Paterniani <a.paterniani@swapp-eng.it>
35 * struct spi_ioc_transfer - describes a single SPI transfer
52 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
53 * Zero-initialize the structure, including currently unused fields, to
65 * in a 16-bit word), the next could read a block of 8-bit data before
67 * could send a different nine bit command (re-selecting the chip), and the
94 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
96 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
102 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
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/Linux-v6.1/drivers/net/ethernet/qlogic/qed/
Dqed_dev.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
11 #include <linux/dma-mapping.h>
72 db_entry->db_addr, in qed_db_recovery_dp_entry()
73 db_entry->db_data, in qed_db_recovery_dp_entry()
74 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", in qed_db_recovery_dp_entry()
75 db_entry->db_space == DB_REC_USER ? "user" : "kernel", in qed_db_recovery_dp_entry()
76 db_entry->hwfn_idx); in qed_db_recovery_dp_entry()
88 if (db_addr < cdev->doorbells || in qed_db_rec_sanity()
[all …]
/Linux-v6.1/tools/memory-model/Documentation/
Dreferences.txt18 o Intel Corporation (Ed.). 2002. "Intel 64 and IA-32 Architectures
22 and Magnus O. Myreen. 2010. "x86-TSO: A Rigorous and Usable
24 (July, 2010), 89-97. http://doi.acm.org/10.1145/1785414.1785443
42 Implementation (PLDI '12). ACM, New York, NY, USA, 311-322.
45 for ARMv8-A architecture profile)". ARM Ltd.
48 For Programmers, Volume II-A: The MIPS64(R) Instruction,
50 LTD. https://imgtec.com/?do-download=4302.
56 SIGPLAN-SIGACT Symposium on Principles of Programming Languages
61 Sewell. 2017. "Mixed-size Concurrency: ARM, POWER, C/C++11,
68 multicopy-atomic axiomatic and operational models for ARMv8". In
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/Linux-v6.1/drivers/crypto/marvell/octeontx/
Dotx_cptpf_mbox.c1 // SPDX-License-Identifier: GPL-2.0
67 get_mbox_opcode_str(mbox_msg->msg), vf_id, in dump_mbox_msg()
71 get_mbox_opcode_str(mbox_msg->msg), raw_data_str); in dump_mbox_msg()
78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
89 mbx->data = 0ull; in otx_cpt_mbox_send_ack()
90 mbx->msg = OTX_CPT_MSG_ACK; in otx_cpt_mbox_send_ack()
98 mbx->data = 0ull; in otx_cptpf_mbox_send_nack()
99 mbx->msg = OTX_CPT_MSG_NACK; in otx_cptpf_mbox_send_nack()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
[all …]
/Linux-v6.1/drivers/dma/idxd/
Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/io-64-nonatomic-lo-hi.h>
26 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_unmask_error_interrupts()
27 genctrl.softerr_int_en = 1; in idxd_unmask_error_interrupts()
28 genctrl.halt_int_en = 1; in idxd_unmask_error_interrupts()
29 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_unmask_error_interrupts()
36 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_mask_error_interrupts()
39 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_mask_error_interrupts()
46 for (i = 0; i < wq->num_descs; i++) in free_hw_descs()
47 kfree(wq->hw_descs[i]); in free_hw_descs()
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