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/Linux-v6.6/drivers/net/phy/
Dbroadcom.c45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()
67 if (rc < 0) in bcm54xx_config_clock_delay()
83 if (rc < 0) in bcm54xx_config_clock_delay()
86 return 0; in bcm54xx_config_clock_delay()
101 return 0; in bcm54210e_config_init()
118 if (err < 0) in bcm54612e_config_init()
122 return 0; in bcm54612e_config_init()
131 return 0; in bcm54616s_config_init()
136 if (val < 0) in bcm54616s_config_init()
142 if (rc < 0) in bcm54616s_config_init()
[all …]
Dbcm7xxx.c20 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22 #define MII_BCM7XXX_100TX_DISC 0x14
23 #define MII_BCM7XXX_AUX_MODE 0x1d
25 #define MII_BCM7XXX_TEST 0x1f
27 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
28 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
29 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30 #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31 #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
[all …]
Ddp83848.c11 #define TI_DP83848C_PHY_ID 0x20005ca0
12 #define TI_DP83620_PHY_ID 0x20005ce0
13 #define NS_DP83848C_PHY_ID 0x20005c90
14 #define TLK10X_PHY_ID 0x2000a210
17 #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
18 #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
21 #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
25 #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
58 return err < 0 ? err : 0; in dp83848_ack_interrupt()
66 if (control < 0) in dp83848_config_intr()
[all …]
Dsmsc.c30 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ 0x0001
34 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ 0x8000
35 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ 0x4000
36 #define SPECIAL_CTRL_STS_AMDIX_STATE_ 0x2000
63 return rc < 0 ? rc : 0; in smsc_phy_ack_interrupt()
78 rc = phy_write(phydev, MII_LAN83C185_IM, 0); in smsc_phy_config_intr()
85 return rc < 0 ? rc : 0; in smsc_phy_config_intr()
106 if (irq_status < 0) { in smsc_phy_handle_interrupt()
127 return 0; in smsc_phy_config_init()
140 if (rc < 0) in smsc_phy_reset()
[all …]
Dlxt.c36 #define MII_LXT970_IER_IEN 0x0002
49 #define MII_LXT971_IER_IEN 0x00f2
52 #define MII_LXT971_ISR_MASK 0x00f0
68 if (err < 0) in lxt970_ack_interrupt()
73 if (err < 0) in lxt970_ack_interrupt()
76 return 0; in lxt970_ack_interrupt()
90 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
108 if (irq_status < 0) { in lxt970_handle_interrupt()
114 if (irq_status < 0) { in lxt970_handle_interrupt()
129 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
[all …]
Ddp83822.c16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
24 #define DP83822_DEVADDR 0x1f
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
[all …]
Dbcm-cygnus.c18 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
26 if (rc < 0) in bcm_cygnus_afe_config()
30 rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); in bcm_cygnus_afe_config()
31 if (rc < 0) in bcm_cygnus_afe_config()
35 rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); in bcm_cygnus_afe_config()
36 if (rc < 0) in bcm_cygnus_afe_config()
40 rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); in bcm_cygnus_afe_config()
41 if (rc < 0) in bcm_cygnus_afe_config()
45 rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); in bcm_cygnus_afe_config()
[all …]
Damd.c16 #define PHY_ID_AM79C874 0x0022561b
19 #define MII_AM79C_IR_EN_LINK 0x0400 /* IR enable Linkstate */
20 #define MII_AM79C_IR_EN_ANEG 0x0100 /* IR enable Aneg Complete */
24 #define MII_AM79C_IR_ANEG_DONE BIT(0)
36 if (err < 0) in am79c_ack_interrupt()
40 if (err < 0) in am79c_ack_interrupt()
43 return 0; in am79c_ack_interrupt()
48 return 0; in am79c_config_init()
62 err = phy_write(phydev, MII_AM79C_IR, 0); in am79c_config_intr()
77 if (irq_status < 0) { in am79c_handle_interrupt()
[all …]
Det1011c.c31 #define ET1011C_STATUS_REG (0x1A)
32 #define ET1011C_CONFIG_REG (0x16)
33 #define ET1011C_SPEED_MASK (0x0300)
34 #define ET1011C_GIGABIT_SPEED (0x0200)
35 #define ET1011C_TX_FIFO_MASK (0x3000)
36 #define ET1011C_TX_FIFO_DEPTH_8 (0x0000)
37 #define ET1011C_TX_FIFO_DEPTH_16 (0x1000)
38 #define ET1011C_INTERFACE_MASK (0x0007)
39 #define ET1011C_GMII_INTERFACE (0x0002)
40 #define ET1011C_SYS_CLK_EN (0x01 << 4)
[all …]
Dste10Xp.c23 #define MII_XCIIS 0x11 /* Configuration Info IRQ & Status Reg */
24 #define MII_XIE 0x12 /* Interrupt Enable Register */
25 #define MII_XIE_DEFAULT_MASK 0x0070 /* ANE complete, Remote Fault, Link Down */
27 #define STE101P_PHY_ID 0x00061c50
28 #define STE100P_PHY_ID 0x1c040011
36 if (value < 0) in ste10Xp_config_init()
41 if (err < 0) in ste10Xp_config_init()
48 return 0; in ste10Xp_config_init()
55 if (err < 0) in ste10Xp_ack_interrupt()
58 return 0; in ste10Xp_ack_interrupt()
[all …]
Dax88796b.c13 #define PHY_ID_ASIX_AX88772A 0x003b1861
14 #define PHY_ID_ASIX_AX88772C 0x003b1881
15 #define PHY_ID_ASIX_AX88796B 0x003b1841
30 * Returns: 0 on success, < 0 on failure
37 ret = phy_write(phydev, MII_BMCR, 0); in asix_soft_reset()
38 if (ret < 0) in asix_soft_reset()
46 * register is 0. This issue is not reproducible on AX88772C.
57 return 0; in asix_ax88772a_read_status()
59 /* If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve in asix_ax88772a_read_status()
63 if (val < 0) in asix_ax88772a_read_status()
[all …]
Dnational.c23 #define DP83865_PHY_ID 0x20005c7a
25 #define DP83865_INT_STATUS 0x14
26 #define DP83865_INT_MASK 0x15
27 #define DP83865_INT_CLEAR 0x17
29 #define DP83865_INT_REMOTE_FAULT 0x0008
30 #define DP83865_INT_ANE_COMPLETED 0x0010
31 #define DP83865_INT_LINK_CHANGE 0xe000
37 #define NS_EXP_MEM_CTL 0x16
38 #define NS_EXP_MEM_DATA 0x1d
39 #define NS_EXP_MEM_ADD 0x1e
[all …]
Dqsemi.c42 #define MII_QS6612_IMR_INIT 0x003a
45 #define QS6612_PCR_AN_COMPLETE 0x1000
46 #define QS6612_PCR_RLBEN 0x0200
47 #define QS6612_PCR_DCREN 0x0100
48 #define QS6612_PCR_4B5BEN 0x0040
49 #define QS6612_PCR_TX_ISOLATE 0x0020
50 #define QS6612_PCR_MLT3_DIS 0x0002
51 #define QS6612_PCR_SCRM_DESCRM 0x0001
57 /* Returns 0, unless there's a write error */
62 * XXX - My docs indicate this should be 0x0940 in qs6612_config_init()
[all …]
Drockchip.c19 #define INTERNAL_EPHY_ID 0x1234d400
37 #define TSTMODE_ENABLE 0x400
38 #define TSTMODE_DISABLE 0x0
40 #define WR_ADDR_A7CFG 0x18
74 * the default value is 0x8. in rockchip_integrated_phy_analog_init()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
95 if (val < 0) in rockchip_integrated_phy_config_init()
127 if (reg < 0) in rockchip_set_polarity()
142 return 0; in rockchip_set_polarity()
152 return 0; in rockchip_set_polarity()
[all …]
/Linux-v6.6/drivers/net/
Dsungem_phy.c37 { 0, 0, 0 }, /* No link */
38 { 0, 0, 0 }, /* 10BT Half Duplex */
39 { 1, 0, 0 }, /* 10BT Full Duplex */
40 { 0, 1, 0 }, /* 100BT Half Duplex */
41 { 0, 1, 0 }, /* 100BT Half Duplex */
42 { 1, 1, 0 }, /* 100BT Full Duplex*/
43 { 1, 0, 1 }, /* 1000BT */
44 { 1, 0, 1 }, /* 1000BT */
81 if ((val & BMCR_RESET) == 0) in reset_one_mii_phy()
85 if ((val & BMCR_ISOLATE) && limit > 0) in reset_one_mii_phy()
[all …]
/Linux-v6.6/include/uapi/linux/netfilter_bridge/
Debt_mark_t.h10 * action 0xfffffff0, the result will look ok for older
12 #define MARK_SET_VALUE (0xfffffff0)
13 #define MARK_OR_VALUE (0xffffffe0)
14 #define MARK_AND_VALUE (0xffffffd0)
15 #define MARK_XOR_VALUE (0xffffffc0)
/Linux-v6.6/arch/mips/loongson2ef/common/cs5536/
Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]
/Linux-v6.6/drivers/atm/
Dnicstarmac.c30 #define CS_HIGH 0x0002 /* Chip select high */
31 #define CS_LOW 0x0000 /* Chip select low (active low) */
32 #define CLK_HIGH 0x0004 /* Clock high */
33 #define CLK_LOW 0x0000 /* Clock low */
34 #define SI_HIGH 0x0001 /* Serial input data high */
35 #define SI_LOW 0x0000 /* Serial input data low */
38 #if 0
42 CLK_HIGH, /* 0 */
44 CLK_HIGH, /* 0 */
46 CLK_HIGH, /* 0 */
[all …]
/Linux-v6.6/net/netfilter/ipset/
Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/Linux-v6.6/include/linux/soc/ixp4xx/
Dcpu.h17 /* Processor id value in CP15 Register 0 */
18 #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
19 #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
21 #define IXP43X_PROCESSOR_ID_VALUE 0x69054040
22 #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
24 #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
25 #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
28 #define IXP4XX_EXP_CNFG2 0x2c
32 #define IXP4XX_FEATURE_RCOMP (1 << 0)
85 #define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
[all …]
/Linux-v6.6/arch/arm/mm/
Dproc-xscale.S59 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
61 #define CLEAN_ADDR 0xfffe0000
69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
116 mrc p15, 0, r1, c1, c0, 1
118 mcr p15, 0, r1, c1, c0, 1
[all …]
/Linux-v6.6/arch/sparc/include/asm/
Dpgtsrmmu.h25 #define SRMMU_ET_MASK 0x3
26 #define SRMMU_ET_INVALID 0x0
27 #define SRMMU_ET_PTD 0x1
28 #define SRMMU_ET_PTE 0x2
29 #define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
32 #define SRMMU_CTX_PMASK 0xfffffff0
33 #define SRMMU_PTD_PMASK 0xfffffff0
34 #define SRMMU_PTE_PMASK 0xffffff00
44 #define SRMMU_CACHE 0x80
45 #define SRMMU_DIRTY 0x40
[all …]
/Linux-v6.6/drivers/net/wireless/ath/ath9k/
Dbtcoex.c45 { 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
46 { 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
47 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
52 { 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
53 { 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
54 { 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
55 { 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */
56 { 0xffffff01, 0xffffffff, 0xffffff01, 0xffffffff }, /* STOMP_AUDIO */
63 .bt_time_extend = 0, in ath9k_hw_init_btcoex_hw()
72 .wl_active_time = 0x20, in ath9k_hw_init_btcoex_hw()
[all …]
/Linux-v6.6/drivers/net/phy/mscc/
Dmscc_main.c103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
128 return 0; in vsc85xx_get_sset_count()
141 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()
153 if (val < 0) in vsc85xx_get_stat()
171 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_stats()
202 return 0; in vsc85xx_mdix_get()
224 reg_val = 0; in vsc85xx_mdix_set()
[all …]
/Linux-v6.6/arch/sh/drivers/pci/
Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]

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