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/Linux-v6.6/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/Linux-v6.6/drivers/gpu/drm/mediatek/
Dmtk_dpi_regs.h9 #define DPI_EN 0x00
10 #define EN BIT(0)
12 #define DPI_RET 0x04
13 #define RST BIT(0)
15 #define DPI_INTEN 0x08
16 #define INT_VSYNC_EN BIT(0)
20 #define DPI_INTSTA 0x0C
21 #define INT_VSYNC_STA BIT(0)
25 #define DPI_CON 0x10
26 #define BG_ENABLE BIT(0)
[all …]
/Linux-v6.6/drivers/gpu/drm/radeon/
Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
/Linux-v6.6/drivers/soc/qcom/
Dllcc-qcom.c21 #define ACTIVATE BIT(0)
23 #define ACT_CLEAR BIT(0)
25 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27 #define ACT_CTRL_ACT_TRIG BIT(0)
28 #define ACT_CTRL_OPCODE_SHIFT 0x01
29 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
30 #define ATTR1_FIXED_SIZE_SHIFT 0x03
31 #define ATTR1_PRIORITY_SHIFT 0x04
32 #define ATTR1_MAX_CAP_SHIFT 0x10
33 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
[all …]
/Linux-v6.6/drivers/media/dvb-frontends/drx39xyj/
Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/Linux-v6.6/drivers/gpu/drm/sun4i/
Dsun4i_tcon.h20 #define SUN4I_TCON_GCTL_REG 0x0
22 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
23 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
24 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
26 #define SUN4I_TCON_GINT0_REG 0x4
34 #define SUN4I_TCON_GINT1_REG 0x8
36 #define SUN4I_TCON_FRM_CTL_REG 0x10
42 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
43 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
44 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
[all …]
/Linux-v6.6/drivers/media/platform/samsung/s5p-g2d/
Dg2d-hw.c27 w(0, SRC_SELECT_REG); in g2d_set_src_size()
28 w(f->stride & 0xFFFF, SRC_STRIDE_REG); in g2d_set_src_size()
30 n = f->o_height & 0xFFF; in g2d_set_src_size()
32 n |= f->o_width & 0xFFF; in g2d_set_src_size()
35 n = f->bottom & 0xFFF; in g2d_set_src_size()
37 n |= f->right & 0xFFF; in g2d_set_src_size()
52 w(0, DST_SELECT_REG); in g2d_set_dst_size()
53 w(f->stride & 0xFFFF, DST_STRIDE_REG); in g2d_set_dst_size()
55 n = f->o_height & 0xFFF; in g2d_set_dst_size()
57 n |= f->o_width & 0xFFF; in g2d_set_dst_size()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/Linux-v6.6/drivers/input/touchscreen/
Dmc13783_ts.c30 "is supposed to be wrong and is discarded. Set to 0 to "
53 schedule_delayed_work(&priv->work, 0); in mc13783_ts_handler()
75 * bits are for future 12 bit use and reading yields 0 in mc13783_ts_report_sample()
77 x0 = priv->sample[0] & 0xfff; in mc13783_ts_report_sample()
78 x1 = priv->sample[1] & 0xfff; in mc13783_ts_report_sample()
79 x2 = priv->sample[2] & 0xfff; in mc13783_ts_report_sample()
80 y0 = priv->sample[3] & 0xfff; in mc13783_ts_report_sample()
81 y1 = (priv->sample[0] >> 12) & 0xfff; in mc13783_ts_report_sample()
82 y2 = (priv->sample[1] >> 12) & 0xfff; in mc13783_ts_report_sample()
83 cr0 = (priv->sample[2] >> 12) & 0xfff; in mc13783_ts_report_sample()
[all …]
/Linux-v6.6/drivers/gpu/host1x/hw/
Dhw_host1x06_hypervisor.h6 #define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
8 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
9 #define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
13 #define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
14 #define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
15 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
16 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
17 #define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
18 #define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
19 #define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
[all …]
Dhw_host1x07_hypervisor.h6 #define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
8 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
9 #define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
13 #define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
14 #define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
15 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
16 #define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
17 #define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
18 #define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
19 #define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
[all …]
Ddebug_hw.c17 HOST1X_OPCODE_SETCLASS = 0x00,
18 HOST1X_OPCODE_INCR = 0x01,
19 HOST1X_OPCODE_NONINCR = 0x02,
20 HOST1X_OPCODE_MASK = 0x03,
21 HOST1X_OPCODE_IMM = 0x04,
22 HOST1X_OPCODE_RESTART = 0x05,
23 HOST1X_OPCODE_GATHER = 0x06,
24 HOST1X_OPCODE_SETSTRMID = 0x07,
25 HOST1X_OPCODE_SETAPPID = 0x08,
26 HOST1X_OPCODE_SETPYLD = 0x09,
[all …]
/Linux-v6.6/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_qp_ctxt.h17 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
18 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
27 #define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
28 #define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
34 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
37 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
38 #define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
44 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
48 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
49 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
[all …]
/Linux-v6.6/drivers/accel/habanalabs/goya/
Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/Linux-v6.6/include/linux/soc/pxa/
Dcpu.h18 * PXA210 B0 0x69052922 0x2926C013
19 * PXA210 B1 0x69052923 0x3926C013
20 * PXA210 B2 0x69052924 0x4926C013
21 * PXA210 C0 0x69052D25 0x5926C013
23 * PXA250 A0 0x69052100 0x09264013
24 * PXA250 A1 0x69052101 0x19264013
25 * PXA250 B0 0x69052902 0x29264013
26 * PXA250 B1 0x69052903 0x39264013
27 * PXA250 B2 0x69052904 0x49264013
28 * PXA250 C0 0x69052D05 0x59264013
[all …]
/Linux-v6.6/drivers/gpu/drm/i915/gvt/
Dfb_decoder.h47 #define _PIPE_V_SRCSZ_SHIFT 0
48 #define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT)
50 #define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT)
53 #define _PRI_PLANE_STRIDE_MASK (0x3ff << 6)
54 #define _PRI_PLANE_X_OFF_SHIFT 0
55 #define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)
57 #define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)
59 #define _CURSOR_MODE 0x3f
61 #define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
63 #define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT)
[all …]
/Linux-v6.6/drivers/gpu/drm/exynos/
Dregs-decon5433.h10 #define DECON_VIDCON0 0x0000
11 #define DECON_VIDOUTCON0 0x0010
12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4))
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
14 #define DECON_SHADOWCON 0x00A0
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
[all …]
/Linux-v6.6/arch/powerpc/platforms/ps3/
Dgelic_udbg.c22 #define GELIC_DEVICE_ID 0
30 #define GELIC_DESCR_DMA_STAT_MASK 0xf0000000
31 #define GELIC_DESCR_DMA_CARDOWNED 0xa0000000
33 #define GELIC_DESCR_TX_DMA_IKE 0x00080000
34 #define GELIC_DESCR_TX_DMA_NO_CHKSUM 0x00000000
35 #define GELIC_DESCR_TX_DMA_FRAME_TAIL 0x00040000
76 u64 real_addr = ((u64)start) & 0x0fffffffffffffffUL; in map_dma_mem()
78 u64 map_start = real_addr & ~0xfff; in map_dma_mem()
79 u64 map_end = (real_end + 0xfff) & ~0xfff; in map_dma_mem()
80 u64 bus_addr = 0; in map_dma_mem()
[all …]
/Linux-v6.6/drivers/accel/habanalabs/gaudi/
Dgaudi_security.c481 while (pb_addr & 0xFFF) { in gaudi_pb_set_block()
482 WREG32(pb_addr, 0); in gaudi_pb_set_block()
505 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
506 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
507 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
508 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
510 WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
511 WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
513 pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_mme_protection_bits()
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowacpi.c35 rom_arg.pointer = &rom_arg_elements[0]; in acpi_read_bios()
37 rom_arg_elements[0].type = ACPI_TYPE_INTEGER; in acpi_read_bios()
38 rom_arg_elements[0].integer.value = offset; in acpi_read_bios()
66 u32 limit = (offset + length + 0xfff) & ~0xfff; in acpi_read_fast()
67 u32 start = offset & ~0x00000fff; in acpi_read_fast()
70 if (nvbios_extend(bios, limit) >= 0) { in acpi_read_fast()
76 return 0; in acpi_read_fast()
87 u32 limit = (offset + length + 0xfff) & ~0xfff; in acpi_read_slow()
88 u32 start = offset & ~0xfff; in acpi_read_slow()
89 u32 fetch = 0; in acpi_read_slow()
[all …]
/Linux-v6.6/drivers/gpu/drm/meson/
Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/Linux-v6.6/drivers/gpu/drm/imx/dcss/
Ddcss-scaler.c13 #define DCSS_SCALER_CTRL 0x00
14 #define SCALER_EN BIT(0)
18 #define DCSS_SCALER_OFIFO_CTRL 0x04
19 #define OFIFO_LOW_THRES_POS 0
20 #define OFIFO_LOW_THRES_MASK GENMASK(9, 0)
29 #define DCSS_SCALER_SDATA_CTRL 0x08
30 #define YUV_EN BIT(0)
35 #define DCSS_SCALER_BIT_DEPTH 0x0C
36 #define LUM_BIT_DEPTH_POS 0
37 #define LUM_BIT_DEPTH_MASK GENMASK(1, 0)
[all …]
/Linux-v6.6/drivers/media/platform/ti/omap3isp/
Disph3a.h27 #define AEWB_SATURATION_LIMIT 0x3ff
30 #define PCR_CHNG (1 << 0)
39 #define ISPH3A_PCR_AF_EN (1 << 0)
56 #define AFPID 0x0
58 #define AFCOEF_OFFSET 0x00000004 /* COEF base address */
63 #define AF_RGBPOS (0x7 << 11)
64 #define AF_MED_TH (0xFF << 3)
67 #define AF_EN (1 << 0)
72 #define AF_PAXW (0x7F << 16)
73 #define AF_PAXH 0x7F
[all …]
/Linux-v6.6/arch/riscv/kernel/
Dmodule.c38 return 0; in apply_r_riscv_32_rela()
44 return 0; in apply_r_riscv_64_rela()
51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
53 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
54 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
57 return 0; in apply_r_riscv_branch_rela()
64 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
65 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/Linux-v6.6/drivers/staging/sm750fb/
Dddk750_reg.h6 #define DE_STATE1 0x100054
7 #define DE_STATE1_DE_ABORT BIT(0)
9 #define DE_STATE2 0x100058
14 #define SYSTEM_CTRL 0x000000
15 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
17 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
19 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
[all …]

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