Searched +full:0 +full:xff290000 (Results 1 – 5 of 5) sorted by relevance
19 reg = <0x0 0xff290000 0x0 0x4000>;
94 description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.98 description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.118 reg = <0xff290000 0x10000>;135 tx_delay = <0x30>;136 rx_delay = <0x10>;
40 #address-cells = <0x2>;41 #size-cells = <0x0>;75 cpu_l0: cpu@0 {78 reg = <0x0 0x0>;86 reg = <0x0 0x1>;94 reg = <0x0 0x2>;102 reg = <0x0 0x3>;110 reg = <0x0 0x100>;118 reg = <0x0 0x101>;126 reg = <0x0 0x102>;[all …]
40 #size-cells = <0>;42 cpu0: cpu@0 {45 reg = <0x0 0x0>;57 reg = <0x0 0x1>;69 reg = <0x0 0x2>;81 reg = <0x0 0x3>;96 arm,psci-suspend-param = <0x0010000>;105 arm,psci-suspend-param = <0x1010000>;113 cpu0_opp_table: opp-table-0 {164 #clock-cells = <0>;[all …]
53 #size-cells = <0>;60 reg = <0x500>;71 reg = <0x501>;82 reg = <0x502>;93 reg = <0x503>;103 cpu_opp_table: opp-table-0 {163 * The rk3288 cannot use the memory area above 0xfe000000173 reg = <0x0 0xfe000000 0x0 0x1000000>;181 #clock-cells = <0>;197 reg = <0x0 0xff810000 0x0 0x20>;[all …]
