Searched +full:0 +full:xff060000 (Results 1 – 6 of 6) sorted by relevance
121 reg = <0xe0008000 0x1000>;126 tx-fifo-depth = <0x40>;127 rx-fifo-depth = <0x40>;133 reg = <0x40000000 0x10000>;134 clocks = <&clkc 0>, <&clkc 1>;138 tx-fifo-depth = <0x40>;139 rx-fifo-depth = <0x40>;145 reg = <0x40000000 0x2000>;146 clocks = <&clkc 0>, <&clkc 1>;150 tx-mailbox-count = <0x20>;[all …]
29 #size-cells = <0>;31 cpu0: cpu@0 {36 reg = <0x0>;45 reg = <0x1>;55 reg = <0x2>;65 reg = <0x3>;80 CPU_SLEEP_0: cpu-sleep-0 {82 arm,psci-suspend-param = <0x40000000>;123 reg = <0x0 0x3ed00000 0x0 0x40000>;128 reg = <0x0 0x3ef00000 0x0 0x40000>;[all …]
33 #define TRCM_TXRX 0135 * Returns success (0) or negative errno.139 int ret = 0; in i2s_tdm_prepare_enable_mclk()162 return 0; in i2s_tdm_prepare_enable_mclk()185 return 0; in i2s_tdm_runtime_suspend()208 return 0; in i2s_tdm_runtime_resume()225 * when clk_trcm > 0.266 unsigned int xfer_mask = 0; in rockchip_snd_xfer_clear()267 unsigned int xfer_val = 0; in rockchip_snd_xfer_clear()333 /* only used when clk_trcm > 0 */[all …]
39 #size-cells = <0>;41 cpu0: cpu@0 {44 reg = <0x0 0x0>;57 reg = <0x0 0x1>;67 reg = <0x0 0x2>;77 reg = <0x0 0x3>;90 arm,psci-suspend-param = <0x0010000>;104 cpu0_opp_table: opp-table-0 {144 #clock-cells = <0>;162 #clock-cells = <0>;[all …]
36 #size-cells = <0>;38 cpu0: cpu@0 {41 reg = <0x0 0x0>;54 reg = <0x0 0x1>;67 reg = <0x0 0x2>;80 reg = <0x0 0x3>;96 arm,psci-suspend-param = <0x0010000>;110 cpu0_opp_table: opp-table-0 {208 #clock-cells = <0>;215 reg = <0x0 0xff000000 0x0 0x1000>;[all …]
40 #size-cells = <0>;42 cpu0: cpu@0 {45 reg = <0x0 0x0>;57 reg = <0x0 0x1>;69 reg = <0x0 0x2>;81 reg = <0x0 0x3>;96 arm,psci-suspend-param = <0x0010000>;105 arm,psci-suspend-param = <0x1010000>;113 cpu0_opp_table: opp-table-0 {164 #clock-cells = <0>;[all …]
