Searched +full:0 +full:xff0000 (Results 1 – 25 of 214) sorted by relevance
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27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x3036 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4[all …]
27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x029 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x031 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x033 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x10034 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x835 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x20036 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9[all …]
27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x029 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x031 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x033 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x78034 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x735 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x180036 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb[all …]
10 EFA_REGS_RESET_NORMAL = 0,24 /* 0 base */25 #define EFA_REGS_VERSION_OFF 0x026 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x427 #define EFA_REGS_CAPS_OFF 0x828 #define EFA_REGS_AQ_BASE_LO_OFF 0x1029 #define EFA_REGS_AQ_BASE_HI_OFF 0x1430 #define EFA_REGS_AQ_CAPS_OFF 0x1831 #define EFA_REGS_ACQ_BASE_LO_OFF 0x2032 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24[all …]
23 * [0] - I/O port base address39 #define PCM3724_8255_0_BASE 0x0040 #define PCM3724_8255_1_BASE 0x0441 #define PCM3724_DIO_DIR_REG 0x0842 #define PCM3724_DIO_DIR_C0_OUT BIT(0)48 #define PCM3724_GATE_CTRL_REG 0x0949 #define PCM3724_GATE_CTRL_C0_ENA BIT(0)65 if (s->io_bits & 0x0000ff) { in compute_buffer()66 if (devno == 0) in compute_buffer()71 if (s->io_bits & 0x00ff00) { in compute_buffer()[all …]
24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
24 #define PDMA0_CORE_CFG_0_EN_SHIFT 025 #define PDMA0_CORE_CFG_0_EN_MASK 0x128 #define PDMA0_CORE_CFG_1_HALT_SHIFT 029 #define PDMA0_CORE_CFG_1_HALT_MASK 0x131 #define PDMA0_CORE_CFG_1_FLUSH_MASK 0x234 #define PDMA0_CORE_PROT_VAL_SHIFT 035 #define PDMA0_CORE_PROT_VAL_MASK 0x137 #define PDMA0_CORE_PROT_ERR_VAL_MASK 0x240 #define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 041 #define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1[all …]
24 #define ARC_FARM_KDMA_CFG_0_EN_SHIFT 025 #define ARC_FARM_KDMA_CFG_0_EN_MASK 0x128 #define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 029 #define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x131 #define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x234 #define ARC_FARM_KDMA_PROT_VAL_SHIFT 035 #define ARC_FARM_KDMA_PROT_VAL_MASK 0x137 #define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x240 #define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 041 #define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1[all …]
24 #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 025 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x128 #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 029 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x131 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x234 #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 035 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x137 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x240 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 041 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1[all …]
24 #define ROT0_KMD_MODE_EN_SHIFT 025 #define ROT0_KMD_MODE_EN_MASK 0x128 #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 029 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x132 #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 033 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF36 #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 037 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF40 #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 041 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF[all …]
27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x128 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x029 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x130 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x031 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x033 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x300000034 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x1835 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x1000000036 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c[all …]
23 #define MME_ARCH_STATUS_A_SHIFT 024 #define MME_ARCH_STATUS_A_MASK 0x126 #define MME_ARCH_STATUS_B_MASK 0x228 #define MME_ARCH_STATUS_CIN_MASK 0x430 #define MME_ARCH_STATUS_COUT_MASK 0x832 #define MME_ARCH_STATUS_TE_MASK 0x1034 #define MME_ARCH_STATUS_LD_MASK 0x2036 #define MME_ARCH_STATUS_ST_MASK 0x4038 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x8040 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100[all …]
20 pattern: "^pmu@[0-9a-f]*"30 - description: Register page 058 reg = <0x2b420000 0x1000>,59 <0x2b430000 0x1000>;61 msi-parent = <&its 0xff0000>;66 reg = <0x2b440000 0x1000>,67 <0x2b450000 0x1000>;69 msi-parent = <&its 0xff0000>;
23 #define DMA0_CORE_CFG_0_EN_SHIFT 024 #define DMA0_CORE_CFG_0_EN_MASK 0x127 #define DMA0_CORE_CFG_1_HALT_SHIFT 028 #define DMA0_CORE_CFG_1_HALT_MASK 0x130 #define DMA0_CORE_CFG_1_FLUSH_MASK 0x232 #define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x435 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 036 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F39 #define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 040 #define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF[all …]
27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]
