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/Linux-v6.1/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-20nm.yaml53 reg = <0xfd922a00 0xd4>,
54 <0xfd922b00 0x2b0>,
55 <0xfd922d80 0x7b>;
61 #phy-cells = <0>;
Ddsi-phy-28nm.yaml52 reg = <0xfd922a00 0xd4>,
53 <0xfd922b00 0x2b0>,
54 <0xfd922d80 0x7b>;
60 #phy-cells = <0>;
/Linux-v6.1/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.c19 .io_offset = 0,
24 .io_start = { 0x4700000, 0x5800000 },
44 .io_start = { 0xfd922800, 0xfd922b00 },
63 .io_start = { 0x1a98000 },
82 .io_start = { 0x1a94000, 0x1a96000 },
101 .io_start = { 0xfd998000, 0xfd9a0000 },
121 .io_start = { 0x994000, 0x996000 },
140 .io_start = { 0xc994000, 0xc996000 },
158 .io_start = { 0xc994000, 0xc996000 },
180 .io_start = { 0xae94000, 0xae96000 },
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm.c39 #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
108 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
133 for (i = 0; i < LPFR_LUT_SIZE; i++) in dsi_pll_28nm_clk_set_rate()
144 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
154 refclk_cfg = 0x0; in dsi_pll_28nm_clk_set_rate()
155 frac_n_mode = 0; in dsi_pll_28nm_clk_set_rate()
169 rem = 0; in dsi_pll_28nm_clk_set_rate()
173 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate()
174 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dqcom-msm8974.dtsi20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
107 reg = <0x0 0x0>;
112 interrupts = <GIC_PPI 7 0xf04>;
121 reg = <0x08000000 0x5100000>;
126 reg = <0x0d100000 0x100000>;
[all …]