Searched +full:0 +full:xfd922b00 (Results 1 – 5 of 5) sorted by relevance
| /Linux-v5.15/Documentation/devicetree/bindings/display/msm/ |
| D | dsi-phy-20nm.yaml | 53 reg = <0xfd922a00 0xd4>,
54 <0xfd922b00 0x2b0>,
55 <0xfd922d80 0x7b>;
61 #phy-cells = <0>;
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| D | dsi-phy-28nm.yaml | 52 reg = <0xfd922a00 0xd4>,
53 <0xfd922b00 0x2b0>,
54 <0xfd922d80 0x7b>;
60 #phy-cells = <0>;
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| /Linux-v5.15/drivers/gpu/drm/msm/dsi/ |
| D | dsi_cfg.c | 13 .io_offset = 0,
24 .io_start = { 0x4700000, 0x5800000 },
44 .io_start = { 0xfd922800, 0xfd922b00 },
63 .io_start = { 0x1a98000 },
82 .io_start = { 0x1a94000, 0x1a96000 },
101 .io_start = { 0xfd998000, 0xfd9a0000 },
121 .io_start = { 0x994000, 0x996000 },
140 .io_start = { 0xc994000, 0xc996000 },
158 .io_start = { 0xc994000, 0xc996000 },
180 .io_start = { 0xae94000, 0xae96000 },
[all …]
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| /Linux-v5.15/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm.c | 39 #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
108 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
133 for (i = 0; i < LPFR_LUT_SIZE; i++) in dsi_pll_28nm_clk_set_rate()
144 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
154 refclk_cfg = 0x0; in dsi_pll_28nm_clk_set_rate()
155 frac_n_mode = 0; in dsi_pll_28nm_clk_set_rate()
169 rem = 0; in dsi_pll_28nm_clk_set_rate()
173 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate()
174 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()
[all …]
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | qcom-msm8974.dtsi | 25 reg = <0x08000000 0x5100000>;
30 reg = <0x0d100000 0x100000>;
35 reg = <0x0d200000 0xa00000>;
40 reg = <0x0dc00000 0x1900000>;
45 reg = <0x0f500000 0x500000>;
50 reg = <0xfa00000 0x200000>;
55 reg = <0x0fc00000 0x160000>;
60 reg = <0x0fd60000 0x20000>;
66 reg = <0x0fd80000 0x180000>;
75 #size-cells = <0>;
[all …]
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