Searched +full:0 +full:xfa00000 (Results 1 – 5 of 5) sorted by relevance
60 reg = <0xfa00000 0x200000>;73 reg = <0xfa00000 0x200000>;94 reg = <0xfc428000 0x4000>;
11 reg = <0x00 0x70000000 0x00 0x10000>;14 ranges = <0x0 0x00 0x70000000 0x10000>;19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */22 <0x01 0x00000000 0x00 0x2000>, /* GICC */23 <0x01 0x00010000 0x00 0x1000>, /* GICH */24 <0x01 0x00020000 0x00 0x2000>; /* GICV */38 reg = <0x00 0x01820000 0x00 0x10000>;39 socionext,synquacer-pre-its = <0x1000000 0x400000>;[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;42 reg = <0x0 0x43000000 0x0 0x20000>;45 ranges = <0x0 0x0 0x43000000 0x20000>;50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */[all …]
21 reg = <0xfa00000 0x200000>;28 #size-cells = <0>;30 cpu@0 {33 reg = <0>;93 reg = <0x0 0x0>;188 interrupts = <GIC_PPI 7 0xf04>;194 #clock-cells = <0>;200 #clock-cells = <0>;207 interrupts = <GIC_PPI 2 0xf08>,208 <GIC_PPI 3 0xf08>,[all …]
20 #clock-cells = <0>;26 #clock-cells = <0>;33 #size-cells = <0>;34 interrupts = <GIC_PPI 9 0xf04>;36 CPU0: cpu@0 {40 reg = <0>;107 reg = <0x0 0x0>;112 interrupts = <GIC_PPI 7 0xf04>;121 reg = <0x08000000 0x5100000>;126 reg = <0x0d100000 0x100000>;[all …]