Searched +full:0 +full:xf000000 (Results 1 – 25 of 59) sorted by relevance
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20 ranges = <0x0 0x10000000 0xf000000>;21 reg = <0x1f400000 0x1000>,22 <0x10000000 0xf000000>;24 lantiq,offset-endianness = <0x4c>;
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x3036 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x836 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x136 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0[all …]
27 #define IH_VMID_0_LUT__PASID_MASK 0xffff28 #define IH_VMID_0_LUT__PASID__SHIFT 0x029 #define IH_VMID_1_LUT__PASID_MASK 0xffff30 #define IH_VMID_1_LUT__PASID__SHIFT 0x031 #define IH_VMID_2_LUT__PASID_MASK 0xffff32 #define IH_VMID_2_LUT__PASID__SHIFT 0x033 #define IH_VMID_3_LUT__PASID_MASK 0xffff34 #define IH_VMID_3_LUT__PASID__SHIFT 0x035 #define IH_VMID_4_LUT__PASID_MASK 0xffff36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0[all …]
27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]
10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x211 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x713 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x514 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x716 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x317 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x1418 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC20 #define NPS_ENET_DISABLE 0[all …]
24 #define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 025 #define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF27 #define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF000030 #define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 031 #define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF34 #define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 035 #define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF37 #define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF000040 #define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 041 #define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF[all …]
24 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 025 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF27 #define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF000030 #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 031 #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF34 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 035 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF37 #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF000040 #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 041 #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF[all …]
65 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"129 pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"156 reg = <0xf000000 0x1000000>;162 gpio-ranges = <&tlmm 0 0 175>;
27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x029 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x031 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x033 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x3034 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x435 #define UVD_SEMA_CMD__MODE_MASK 0x4036 #define UVD_SEMA_CMD__MODE__SHIFT 0x6[all …]
20 #define AR_MCI_COMMAND0 0x180021 #define AR_MCI_COMMAND0_HEADER 0xFF22 #define AR_MCI_COMMAND0_HEADER_S 023 #define AR_MCI_COMMAND0_LEN 0x1f0025 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x200028 #define AR_MCI_COMMAND1 0x180430 #define AR_MCI_COMMAND2 0x180831 #define AR_MCI_COMMAND2_RESET_TX 0x0132 #define AR_MCI_COMMAND2_RESET_TX_S 033 #define AR_MCI_COMMAND2_RESET_RX 0x02[all …]
18 #define AQ_ACCESS_MAC 0x0119 #define AQ_FLASH_PARAMETERS 0x2020 #define AQ_PHY_POWER 0x3121 #define AQ_WOL_CFG 0x6022 #define AQ_PHY_OPS 0x6143 #define SFR_GENERAL_STATUS 0x0344 #define SFR_CHIP_STATUS 0x0545 #define SFR_RX_CTL 0x0B46 #define SFR_RX_CTL_TXPADCRC 0x040047 #define SFR_RX_CTL_IPE 0x0200[all …]
27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x128 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x029 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x130 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x031 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x033 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x300000034 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x1835 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x1000000036 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c[all …]
9 #size-cells = <0>;13 cpu@0 {16 reg = <0>;31 #address-cells = <0>;41 #clock-cells = <0>;47 #clock-cells = <0>;57 ranges = <0 0x10000000 0x01000000>;61 reg = <0x441400 0x30>, <0x441600 0x30>;72 reg = <0x401800 0x30>;81 reg = <0x400000 0xdc>;[all …]
