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/Linux-v5.15/arch/arm64/boot/dts/ti/
Dk3-j721e-som-p0.dtsi14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
Dk3-am642-sk.dts20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
26 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
36 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
37 alignment = <0x1000>;
43 reg = <0x00 0xa0000000 0x00 0x100000>;
49 reg = <0x00 0xa0100000 0x00 0xf00000>;
55 reg = <0x00 0xa1000000 0x00 0x100000>;
61 reg = <0x00 0xa1100000 0x00 0xf00000>;
67 reg = <0x00 0xa2000000 0x00 0x100000>;
73 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
Dk3-am642-evm.dts21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
38 alignment = <0x1000>;
44 reg = <0x00 0xa0000000 0x00 0x100000>;
50 reg = <0x00 0xa0100000 0x00 0xf00000>;
56 reg = <0x00 0xa1000000 0x00 0x100000>;
62 reg = <0x00 0xa1100000 0x00 0xf00000>;
68 reg = <0x00 0xa2000000 0x00 0x100000>;
74 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mtd/partitions/
Dbrcm,bcm4908-partitions.yaml31 "^partition@[0-9a-f]+$":
51 partition@0 {
53 reg = <0x0 0x100000>;
58 reg = <0x100000 0xf00000>;
63 reg = <0x1000000 0xf00000>;
68 reg = <0x1f00000 0x100000>;
Dlinksys,ns-partitions.yaml32 "^partition@[0-9a-f]+$":
54 partition@0 {
56 reg = <0x0 0x100000>;
62 reg = <0x100000 0x100000>;
67 reg = <0x200000 0xf00000>;
72 reg = <0x1100000 0xf00000>;
Dnvmem-cells.yaml43 reg = <0x1200000 0x0140000>;
49 macaddr_gmac1: macaddr_gmac1@0 {
50 reg = <0x0 0x6>;
54 reg = <0x6 0x6>;
58 reg = <0x1000 0x2f20>;
62 reg = <0x5000 0x2f20>;
71 partition@0 {
73 reg = <0x000000 0x100000>;
80 reg = <0x100000 0xe00000>;
86 reg = <0xf00000 0x100000>;
[all …]
Dfixed-partitions.yaml29 "@[0-9a-f]+$":
45 partition@0 {
47 reg = <0x0000000 0x100000>;
52 reg = <0x0100000 0x200000>;
62 partition@0 {
64 reg = <0x00000000 0x1 0x00000000>;
74 partition@0 {
76 reg = <0x0 0x00000000 0x2 0x00000000>;
82 reg = <0x2 0x00000000 0x1 0x00000000>;
91 partition@0 {
[all …]
/Linux-v5.15/arch/arm64/boot/dts/marvell/
Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
Dcn9130.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
23 0xe0000000 + ((iface - 1) * 0x1000000))
24 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
Darmada-70x0.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: m25p80@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/Linux-v5.15/tools/perf/tests/
Dhists_common.h12 #define FAKE_MAP_PERF 0x400000
13 #define FAKE_MAP_BASH 0x400000
14 #define FAKE_MAP_LIBC 0x500000
15 #define FAKE_MAP_KERNEL 0xf00000
16 #define FAKE_MAP_LENGTH 0x100000
/Linux-v5.15/drivers/comedi/drivers/
Dcomedi_8255.c24 * digital I/O subdevice with 24 channels. The channel 0 corresponds to
25 * the 8255's port A, bit 0; channel 23 corresponds to port C, bit 7.
26 * Direction configuration is done in blocks, with channels 0-7, 8-15,
28 * supported is mode 0.
47 return 0; in subdev_8255_io()
57 return 0; in subdev_8255_mmio()
74 if (mask & 0xff) in subdev_8255_insn()
76 s->state & 0xff, regbase); in subdev_8255_insn()
77 if (mask & 0xff00) in subdev_8255_insn()
79 (s->state >> 8) & 0xff, regbase); in subdev_8255_insn()
[all …]
/Linux-v5.15/arch/mips/boot/dts/netlogic/
Dxlp_rvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
Dxlp_gvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
/Linux-v5.15/include/rdma/
Dopa_addr.h11 #define OPA_SPECIAL_OUI (0x00066AULL)
14 ? 0 : x)
15 #define OPA_GID_INDEX 0x1
17 * 0xF8 - 4 bits of multicast range and 1 bit for collective range
19 * Multicast range: 0xF00000 to 0xF7FFFF
20 * Collective range: 0xF80000 to 0xFFFFFE
22 #define OPA_MCAST_NR 0x4 /* Number of top bits set */
23 #define OPA_COLLECTIVE_NR 0x1 /* Number of bits after MCAST_NR */
48 return be64_to_cpu(gid->global.interface_id) & 0xFFFFFFFF; in opa_get_lid_from_gid()

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