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Searched +full:0 +full:xe6180000 (Results 1 – 25 of 29) sorted by relevance

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/Linux-v5.15/arch/arm/mach-shmobile/
Dsmp-sh73a0.c19 #define CPG_BASE2 0xe6151000
20 #define WUPCR 0x10 /* System-CPU Wake Up Control Register */
21 #define SRESCR 0x18 /* System-CPU Software Reset Control Register */
22 #define PSTR 0x40 /* System-CPU Power Status Register */
24 #define SYSC_BASE 0xe6180000
25 #define SBAR 0x20 /* SYS Boot Address Register */
27 #define AP_BASE 0xe6f10000
28 #define APARMBAREA 0x20 /* Address Translation Area Register */
30 #define SH73A0_SCU_BASE 0xf0000000
42 return 0; in sh73a0_boot_secondary()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/power/
Drenesas,rcar-sysc.yaml63 reg = <0xe6180000 0x0200>;
71 cache-controller-0 {
Drenesas,sysc-rmobile.yaml45 const: 0
77 const: 0
80 const: 0
95 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
100 #size-cells = <0>;
101 #power-domain-cells = <0>;
106 #size-cells = <0>;
107 #power-domain-cells = <0>;
111 #power-domain-cells = <0>;
117 #power-domain-cells = <0>;
/Linux-v5.15/arch/arm/boot/dts/
Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
[all …]
Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
97 #clock-cells = <0>;
99 clock-frequency = <0>;
[all …]
Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
Dr8a77470.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
51 L2_CA7: cache-controller-0 {
62 #clock-cells = <0>;
64 clock-frequency = <0>;
77 #clock-cells = <0>;
79 clock-frequency = <0>;
93 reg = <0 0xe6020000 0 0x0c>;
103 reg = <0 0xe6050000 0 0x50>;
[all …]
Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dr8a77970.dtsi30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #size-cells = <0>;
38 a53_0: cpu@0 {
41 reg = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
77 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
Dr8a779a0.dtsi29 #size-cells = <0>;
31 a76_0: cpu@0 {
33 reg = <0>;
39 L3_CA76_0: cache-controller-0 {
49 #clock-cells = <0>;
51 clock-frequency = <0>;
56 #clock-cells = <0>;
58 clock-frequency = <0>;
69 #clock-cells = <0>;
70 clock-frequency = <0>;
[all …]
Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]
Dr8a77980.dtsi31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #size-cells = <0>;
39 a53_0: cpu@0 {
42 reg = <0>;
89 #clock-cells = <0>;
91 clock-frequency = <0>;
96 #clock-cells = <0>;
98 clock-frequency = <0>;
104 #clock-cells = <0>;
[all …]
Dr8a77990.dtsi29 * The external audio clocks are configured as 0 Hz fixed frequency
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
81 #size-cells = <0>;
[all …]
Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
Dr8a774a1.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
106 #size-cells = <0>;
[all …]
Dr8a77965.dtsi36 * The external audio clocks are configured as 0 Hz fixed frequency
42 #clock-cells = <0>;
43 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
107 #size-cells = <0>;
[all …]
Dr8a774b1.dtsi21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
[all …]

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