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12

/Linux-v6.1/arch/mips/jazz/
Dirq.c62 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); in init_r4030_ints()
69 * driver compatibility reasons interrupts 0 - 15 to be the i8259
79 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in arch_init_irq()
80 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in arch_init_irq()
81 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ in arch_init_irq()
82 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); in arch_init_irq()
83 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ in arch_init_irq()
84 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); in arch_init_irq()
106 if (likely(irq > 0)) in plat_irq_dispatch()
Dsetup.c33 .start = 0x00,
34 .end = 0x1f,
38 .start = 0x40,
39 .end = 0x5f,
43 .start = 0x80,
44 .end = 0x8f,
48 .start = 0xc0,
49 .end = 0xdf,
59 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in plat_mem_setup()
60 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in plat_mem_setup()
[all …]
/Linux-v6.1/arch/arm/mach-bcm/
Dboard_bcm281xx.c11 #define SECWDOG_OFFSET 0x00000000
12 #define SECWDOG_RESERVED_MASK 0xe2000000
13 #define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000
14 #define SECWDOG_EN_MASK 0x08000000
15 #define SECWDOG_SRSTEN_MASK 0x04000000
17 #define SECWDOG_COUNT_SHIFT 0
30 base = of_iomap(np_wdog, 0); in bcm281xx_restart()
41 (0x15 << SECWDOG_CLKS_SHIFT) | in bcm281xx_restart()
42 (0x8 << SECWDOG_COUNT_SHIFT); in bcm281xx_restart()
/Linux-v6.1/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Darm,pl353-nand-r2p1.yaml38 reg = <0xe000e000 0x0001000>;
41 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
42 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
43 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
47 nfc0: nand-controller@0,0 {
49 reg = <0 0 0x1000000>;
51 #size-cells = <0>;
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0xf 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
28 ranges = <0 0xf 0xe0000000 0x100000>;
32 reg = <0xf 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 reg = <0xf 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
[all …]
Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 reg = <0 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
[all …]
Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
Dmpc8540ads.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8541cds.dts29 #size-cells = <0>;
31 PowerPC,8541@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8555cds.dts29 #size-cells = <0>;
31 PowerPC,8555@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Darm,pl353-smc.yaml29 pattern: "^memory-controller@[0-9a-f]+$"
63 <cs-number> 0 <offset> <size>
65 - description: NAND bank 0
66 - description: NOR/SRAM bank 0
72 "@[0-3],[a-f0-9]+$":
89 minimum: 0
115 reg = <0xe000e000 0x0001000>;
118 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
119 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
120 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dmicrochip,lan966x-switch.yaml20 pattern: "^switch@[0-9a-f]+$"
68 const: 0
73 "^port@[0-9a-f]+$":
83 const: 0
143 reg = <0xe0000000 0x0100000>,
144 <0xe2000000 0x0800000>;
148 resets = <&switch_reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
155 reg = <0>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/marvell/
Dcn9131-db.dtsi21 cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
45 pinctrl-0 = <&cp1_sfp_pins>;
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
90 phys = <&cp1_comphy4 0>;
106 pinctrl-0 = <&cp1_i2c0_pins>;
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
119 phys = <&cp1_comphy0 0
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dspear600.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
23 reg = <0 0x40000000>;
30 ranges = <0xd0000000 0xd0000000 0x30000000>;
35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
64 reg = <0xe0800000 0x8000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
[all …]
Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04
43 0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
/Linux-v6.1/arch/mips/include/asm/
Djazz.h15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
28 #define PICA_ASIC_REVISION 0xe0000008
43 * --------- . (0)
45 #define PICA_LED 0xe000f000
54 #define LED_DOT 0x01
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dstx_gp3_8560.dts27 #size-cells = <0>;
29 PowerPC,8560@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0 0xfdf00000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]

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