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/Linux-v5.15/Documentation/devicetree/bindings/mtd/
Darm,pl353-nand-r2p1.yaml38 reg = <0xe000e000 0x0001000>;
41 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
42 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
43 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
47 nfc0: nand-controller@0,0 {
49 reg = <0 0 0x1000000>;
51 #size-cells = <0>;
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Darm,pl353-smc.yaml29 pattern: "^memory-controller@[0-9a-f]+$"
63 <cs-number> 0 <offset> <size>
65 - description: NAND bank 0
66 - description: NOR/SRAM bank 0
72 "@[0-3],[a-f0-9]+$":
89 minimum: 0
115 reg = <0xe000e000 0x0001000>;
118 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
119 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
120 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
[all …]
/Linux-v5.15/drivers/mcb/
Dmcb-lpc.c26 int ret = 0; in mcb_lpc_probe()
32 priv->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mcb_lpc_probe()
60 if (ret < 0) { in mcb_lpc_probe()
69 return 0; in mcb_lpc_probe()
79 return 0; in mcb_lpc_remove()
101 return 0; in mcb_lpc_create_platform_device()
108 static struct resource sc24_fpga_resource = DEFINE_RES_MEM(0xe000e000, CHAM_HEADER_SIZE);
109 static struct resource sc31_fpga_resource = DEFINE_RES_MEM(0xf000e000, CHAM_HEADER_SIZE);
/Linux-v5.15/arch/arm/boot/dts/
Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
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/Linux-v5.15/drivers/media/platform/rockchip/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]