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/Linux-v6.6/drivers/pinctrl/sunxi/
Dpinctrl-sun20i-d1.c18 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
19 SUNXI_FUNCTION(0x0, "gpio_in"),
20 SUNXI_FUNCTION(0x1, "gpio_out"),
21 SUNXI_FUNCTION(0x2, "pwm3"),
22 SUNXI_FUNCTION(0x3, "ir"), /* TX */
23 SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
24 SUNXI_FUNCTION(0x5, "spi1"), /* WP */
25 SUNXI_FUNCTION(0x6, "uart0"), /* TX */
26 SUNXI_FUNCTION(0x7, "uart2"), /* TX */
27 SUNXI_FUNCTION(0x8, "spdif"), /* OUT */
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/umc/
Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/Linux-v6.6/arch/mips/math-emu/
Dieee754dp.c65 xm += 0x3 + ((xm >> 3) & 1); in ieee754dp_get_rounding()
66 /* xm += (xm&0x8)?0x4:0x3 */ in ieee754dp_get_rounding()
70 xm += 0x8; in ieee754dp_get_rounding()
74 xm += 0x8; in ieee754dp_get_rounding()
84 * xe is an unbiased exponent
87 union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) in ieee754dp_format() argument
91 assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */ in ieee754dp_format()
94 if (xe < DP_EMIN) { in ieee754dp_format()
96 int es = DP_EMIN - xe; in ieee754dp_format()
107 if (sn == 0) in ieee754dp_format()
[all …]
Dieee754sp.c65 xm += 0x3 + ((xm >> 3) & 1); in ieee754sp_get_rounding()
66 /* xm += (xm&0x8)?0x4:0x3 */ in ieee754sp_get_rounding()
70 xm += 0x8; in ieee754sp_get_rounding()
74 xm += 0x8; in ieee754sp_get_rounding()
84 * xe is an unbiased exponent
87 union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm) in ieee754sp_format() argument
91 assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */ in ieee754sp_format()
94 if (xe < SP_EMIN) { in ieee754sp_format()
96 int es = SP_EMIN - xe; in ieee754sp_format()
107 if (sn == 0) in ieee754sp_format()
[all …]
Ddp_tlong.c37 return 0; in ieee754dp_tlong()
43 if (xe >= 63) { in ieee754dp_tlong()
45 if (xe == 63 && xs && xm == DP_HIDDEN_BIT) in ieee754dp_tlong()
46 return -0x8000000000000000LL; in ieee754dp_tlong()
53 if (xe > DP_FBITS) { in ieee754dp_tlong()
54 xm <<= xe - DP_FBITS; in ieee754dp_tlong()
55 } else if (xe < DP_FBITS) { in ieee754dp_tlong()
56 if (xe < -1) { in ieee754dp_tlong()
58 round = 0; in ieee754dp_tlong()
59 sticky = residue != 0; in ieee754dp_tlong()
[all …]
Dsp_tint.c37 return 0; in ieee754sp_tint()
43 if (xe >= 31) { in ieee754sp_tint()
45 if (xe == 31 && xs && xm == SP_HIDDEN_BIT) in ieee754sp_tint()
46 return -0x80000000; in ieee754sp_tint()
53 if (xe > SP_FBITS) { in ieee754sp_tint()
54 xm <<= xe - SP_FBITS; in ieee754sp_tint()
56 if (xe < -1) { in ieee754sp_tint()
58 round = 0; in ieee754sp_tint()
59 sticky = residue != 0; in ieee754sp_tint()
60 xm = 0; in ieee754sp_tint()
[all …]
Dsp_tlong.c37 return 0; in ieee754sp_tlong()
43 if (xe >= 63) { in ieee754sp_tlong()
45 if (xe == 63 && xs && xm == SP_HIDDEN_BIT) in ieee754sp_tlong()
46 return -0x8000000000000000LL; in ieee754sp_tlong()
53 if (xe > SP_FBITS) { in ieee754sp_tlong()
54 xm <<= xe - SP_FBITS; in ieee754sp_tlong()
55 } else if (xe < SP_FBITS) { in ieee754sp_tlong()
56 if (xe < -1) { in ieee754sp_tlong()
58 round = 0; in ieee754sp_tlong()
59 sticky = residue != 0; in ieee754sp_tlong()
[all …]
Ddp_sub.c104 /* normalize xm,xe */ in ieee754dp_sub()
122 if (xe > ye) { in ieee754dp_sub()
126 s = xe - ye; in ieee754dp_sub()
129 } else if (ye > xe) { in ieee754dp_sub()
133 s = ye - xe; in ieee754dp_sub()
135 xe += s; in ieee754dp_sub()
137 assert(xe == ye); in ieee754dp_sub()
138 assert(xe <= DP_EMAX); in ieee754dp_sub()
147 xe++; in ieee754dp_sub()
156 if (xm == 0) { in ieee754dp_sub()
[all …]
Ddp_add.c116 if (xe > ye) { in ieee754dp_add()
120 s = xe - ye; in ieee754dp_add()
123 } else if (ye > xe) { in ieee754dp_add()
127 s = ye - xe; in ieee754dp_add()
129 xe += s; in ieee754dp_add()
131 assert(xe == ye); in ieee754dp_add()
132 assert(xe <= DP_EMAX); in ieee754dp_add()
137 * leaving result in xm, xs and xe. in ieee754dp_add()
143 xe++; in ieee754dp_add()
152 if (xm == 0) in ieee754dp_add()
[all …]
Ddp_tint.c37 return 0; in ieee754dp_tint()
43 if (xe > 31) { in ieee754dp_tint()
50 if (xe > DP_FBITS) { in ieee754dp_tint()
51 xm <<= xe - DP_FBITS; in ieee754dp_tint()
52 } else if (xe < DP_FBITS) { in ieee754dp_tint()
53 if (xe < -1) { in ieee754dp_tint()
55 round = 0; in ieee754dp_tint()
56 sticky = residue != 0; in ieee754dp_tint()
57 xm = 0; in ieee754dp_tint()
59 residue = xm << (64 - DP_FBITS + xe); in ieee754dp_tint()
[all …]
Dsp_add.c116 if (xe > ye) { in ieee754sp_add()
120 s = xe - ye; in ieee754sp_add()
123 } else if (ye > xe) { in ieee754sp_add()
127 s = ye - xe; in ieee754sp_add()
129 xe += s; in ieee754sp_add()
131 assert(xe == ye); in ieee754sp_add()
132 assert(xe <= SP_EMAX); in ieee754sp_add()
137 * leaving result in xm, xs and xe. in ieee754sp_add()
151 if (xm == 0) in ieee754sp_add()
157 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_add()
[all …]
Dsp_sub.c120 if (xe > ye) { in ieee754sp_sub()
124 s = xe - ye; in ieee754sp_sub()
127 } else if (ye > xe) { in ieee754sp_sub()
131 s = ye - xe; in ieee754sp_sub()
133 xe += s; in ieee754sp_sub()
135 assert(xe == ye); in ieee754sp_sub()
136 assert(xe <= SP_EMAX); in ieee754sp_sub()
153 if (xm == 0) { in ieee754sp_sub()
157 return ieee754sp_zero(0); /* other round modes => sign = 1 */ in ieee754sp_sub()
161 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_sub()
[all …]
Dieee754int.h18 MADDF_NEGATE_PRODUCT = 1 << 0,
24 ieee754_csr.cx = 0; in ieee754_clearcx()
46 unsigned int xm; int xe; int xs __maybe_unused; int xc
60 if (vm == 0) \
78 #define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
84 u64 xm; int xe; int xs __maybe_unused; int xc
98 if (vm == 0) \
116 #define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
126 vm = 0; \
137 vm = 0; \
[all …]
Ddp_fint.c15 int xe; in ieee754dp_fint() local
20 if (x == 0) in ieee754dp_fint()
21 return ieee754dp_zero(0); in ieee754dp_fint()
23 return ieee754dp_one(x < 0); in ieee754dp_fint()
25 return ieee754dp_ten(x < 0); in ieee754dp_fint()
27 xs = (x < 0); in ieee754dp_fint()
38 xe = DP_FBITS; in ieee754dp_fint()
39 while ((xm >> DP_FBITS) == 0) { in ieee754dp_fint()
41 xe--; in ieee754dp_fint()
43 return builddp(xs, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); in ieee754dp_fint()
Ddp_flong.c15 int xe; in ieee754dp_flong() local
20 if (x == 0) in ieee754dp_flong()
21 return ieee754dp_zero(0); in ieee754dp_flong()
23 return ieee754dp_one(x < 0); in ieee754dp_flong()
25 return ieee754dp_ten(x < 0); in ieee754dp_flong()
27 xs = (x < 0); in ieee754dp_flong()
38 xe = DP_FBITS + 3; in ieee754dp_flong()
46 while ((xm >> (DP_FBITS + 3)) == 0) { in ieee754dp_flong()
48 xe--; in ieee754dp_flong()
52 return ieee754dp_format(xs, xe, xm); in ieee754dp_flong()
Dsp_fint.c15 int xe; in ieee754sp_fint() local
20 if (x == 0) in ieee754sp_fint()
21 return ieee754sp_zero(0); in ieee754sp_fint()
23 return ieee754sp_one(x < 0); in ieee754sp_fint()
25 return ieee754sp_ten(x < 0); in ieee754sp_fint()
27 xs = (x < 0); in ieee754sp_fint()
36 xe = SP_FBITS + 3; in ieee754sp_fint()
47 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_fint()
49 xe--; in ieee754sp_fint()
52 return ieee754sp_format(xs, xe, xm); in ieee754sp_fint()
Dsp_flong.c15 int xe; in ieee754sp_flong() local
20 if (x == 0) in ieee754sp_flong()
21 return ieee754sp_zero(0); in ieee754sp_flong()
23 return ieee754sp_one(x < 0); in ieee754sp_flong()
25 return ieee754sp_ten(x < 0); in ieee754sp_flong()
27 xs = (x < 0); in ieee754sp_flong()
36 xe = SP_FBITS + 3; in ieee754sp_flong()
46 while ((xm >> (SP_FBITS + 3)) == 0) { in ieee754sp_flong()
48 xe--; in ieee754sp_flong()
51 return ieee754sp_format(xs, xe, xm); in ieee754sp_flong()
/Linux-v6.6/Documentation/gpu/rfc/
Dxe.rst2 Xe – Merge Acceptance Plan
4 Xe is a new driver for Intel GPUs that supports both integrated and
5 discrete platforms starting with Tiger Lake (first Intel Xe Architecture).
7 This document aims to establish a merge plan for the Xe, by writing down clear
10 Xe – Overview
12 The main motivation of Xe is to have a fresh base to work from that is
38 https://gitlab.freedesktop.org/drm/xe/kernel (branch drm-xe-next)
40 Xe – Platforms
42 Currently, Xe is already functional and has experimental support for multiple
47 During a transition period, platforms will be supported by both Xe and i915.
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
/Linux-v6.6/drivers/ata/pata_parport/
Daten.c20 #define j44(a,b) ((((a>>4)&0x0f)|(b&0xf0))^0x88)
23 * cont = 0 - access the IDE register file
26 static int cont_map[2] = { 0x08, 0x20 };
30 int r = regr + cont_map[cont] + 0x80; in aten_write_regr()
32 w0(r); w2(0xe); w2(6); w0(val); w2(7); w2(6); w2(0xc); in aten_write_regr()
39 r = regr + cont_map[cont] + 0x40; in aten_read_regr()
43 case 0: in aten_read_regr()
44 w0(r); w2(0xe); w2(6); in aten_read_regr()
45 w2(7); w2(6); w2(0); in aten_read_regr()
46 a = r1(); w0(0x10); b = r1(); w2(0xc); in aten_read_regr()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/athub/
Dathub_3_0_0_sh_mask.h29 …R_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
30 …RTR0__BASE_ADDR_MASK 0x7FFFFFFFL
32 …R_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
33 …RTR1__BASE_ADDR_MASK 0x7FFFFFFFL
35 …R_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
36 …RTR2__BASE_ADDR_MASK 0x7FFFFFFFL
38 …R_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
39 …RTR3__BASE_ADDR_MASK 0x7FFFFFFFL
41 …R_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
42 …RTR4__BASE_ADDR_MASK 0x7FFFFFFFL
[all …]
Dathub_1_8_0_sh_mask.h29 …S_CNTL__DISABLE_ATC__SHIFT 0x0
30 …S_CNTL__DISABLE_PRI__SHIFT 0x1
31 …S_CNTL__DISABLE_PASID__SHIFT 0x2
32 …S_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
33 …_CNTL__DEBUG_ECO__SHIFT 0x10
34 …_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
35 …DISABLE_ATC_MASK 0x00000001L
36 …DISABLE_PRI_MASK 0x00000002L
37 …DISABLE_PASID_MASK 0x00000004L
38 …CREDITS_ATS_RPB_MASK 0x00003F00L
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/Linux-v6.6/drivers/iio/dac/
Dad7293.c27 #define AD7293_REG_NO_OP (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
28 #define AD7293_REG_PAGE_SELECT (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
29 #define AD7293_REG_CONV_CMD (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
30 #define AD7293_REG_RESULT (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
31 #define AD7293_REG_DAC_EN (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
32 #define AD7293_REG_DEVICE_ID (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
33 #define AD7293_REG_SOFT_RESET (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
35 /* AD7293 Register Map Page 0x0 */
36 #define AD7293_REG_VIN0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
37 #define AD7293_REG_VIN1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]

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