Searched +full:0 +full:xd0100000 (Results 1 – 8 of 8) sorted by relevance
18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)[all …]
14 #address-cells = <0>;15 #size-cells = <0>;25 reg = <0 0x40000000>;32 ranges = <0xd0000000 0xd0000000 0x30000000>;37 reg = <0xf1100000 0x1000>;43 reg = <0xfc400000 0x1000>;51 reg = <0xe0800000 0x8000>;62 reg = <0xfc000000 0x1000>;69 reg = <0xd0100000 0x1000>;72 #size-cells = <0>;[all …]
17 reg = <0xe0700000 0x1000>;18 st-spics,peripcfg-reg = <0x42c>;30 reg = <0xeb800000 0x4000>;38 reg = <0xb1000000 0x10000>;39 interrupts = <0 72 0x4>;40 phys = <&miphy0 0>;47 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;49 interrupts = <0 68 0x4>;56 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */57 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */[all …]
89 port@0:103 const: 0109 - port@0121 reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;125 #size-cells = <0>;129 port@0 {130 reg = <0>;
35 hwrom_reserved: hwrom@0 {36 reg = <0x0 0x0 0x0 0x1000000>;42 reg = <0x0 0x10000000 0x0 0x200000>;48 reg = <0x0 0x05000000 0x0 0x300000>;54 reg = <0x0 0x05300000 0x0 0x2000000>;61 size = <0x0 0x10000000>;62 alignment = <0x0 0x400000>;90 #address-cells = <0x2>;91 #size-cells = <0x0>;93 cpu0: cpu@0 {[all …]
27 // base address: 0x028 …BIF_BX_PF_MM_INDEX 0x000029 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 030 …BIF_BX_PF_MM_DATA 0x000131 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 032 …BIF_BX_PF_MM_INDEX_HI 0x000633 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 037 // base address: 0x038 …SYSHUB_INDEX_OVLP 0x000839 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0[all …]
29 // base address: 0x030 …BIF_BX0_PCIE_INDEX 0x000c31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 032 …BIF_BX0_PCIE_DATA 0x000d33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 034 …BIF_BX0_PCIE_INDEX2 0x000e35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 036 …BIF_BX0_PCIE_DATA2 0x000f37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 038 …BIF_BX0_PCIE_INDEX_HI 0x0010[all …]
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 025 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000031 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 033 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF000042 #define PIN_CFG_NA 0x0000000043 #define PIN_CFG_GPIO0_P0 0x0000000144 #define PIN_CFG_GPIO1_P0 0x00000002[all …]
