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/Linux-v6.1/drivers/thunderbolt/
Dxdomain.c80 UUID_INIT(0xb638d70e, 0x42ff, 0x40bb,
81 0x97, 0xc2, 0x90, 0xe2, 0xc0, 0xb2, 0xff, 0x07);
125 req->result.err = 0; in tb_xdomain_copy()
154 * @xd: XDomain to send the message
162 * Return: %0 in case of success and negative errno in case of failure
164 int tb_xdomain_response(struct tb_xdomain *xd, const void *response, in tb_xdomain_response() argument
167 return __tb_xdomain_response(xd->tb->ctl, response, size, type); in tb_xdomain_response()
201 * @xd: XDomain to send the request
214 * Return: %0 in case of success and negative errno in case of failure
216 int tb_xdomain_request(struct tb_xdomain *xd, const void *request, in tb_xdomain_request() argument
[all …]
Dicm.c26 #define PCIE2CIO_CMD 0x30
35 #define PCIE2CIO_WRDATA 0x34
36 #define PCIE2CIO_RDDATA 0x38
38 #define PHY_PORT_CS1 0x37
73 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported)
136 #define EP_NAME_INTEL_VSS 0x10
148 #define INTEL_VSS_FLAGS_RTD3 BIT(0)
197 return link ? ((link - 1) ^ 0x01) + 1 : 0; in dual_link_from_link()
208 return depth ? route & ~(0xffULL << (depth - 1) * TB_ROUTE_SHIFT) : 0; in get_parent_route()
222 return 0; in pci2cio_wait_completion()
[all …]
Ddma_test.c19 #define DMA_TEST_DATA_PATTERN 0x0123456789abcdefLL
72 * @xd: XDomain the service belongs to
81 * @link_speed: Expected link speed (Gb/s), %0 to use whatever is negotiated
82 * @link_width: Expected link width (Gb/s), %0 to use whatever is negotiated
94 struct tb_xdomain *xd; member
116 UUID_INIT(0x3188cd10, 0x6523, 0x4a5a,
117 0xa6, 0x82, 0xfd, 0xca, 0x07, 0xa2, 0x48, 0xd8);
125 tb_xdomain_release_in_hopid(dt->xd, dt->rx_hopid); in dma_test_free_rings()
130 tb_xdomain_release_out_hopid(dt->xd, dt->tx_hopid); in dma_test_free_rings()
139 struct tb_xdomain *xd = dt->xd; in dma_test_start_rings() local
[all …]
/Linux-v6.1/fs/jffs2/
Dxattr.c32 * is_xattr_datum_unchecked(c, xd)
34 * unchecked, it returns 0.
35 * unload_xattr_datum(c, xd)
41 * do_verify_xattr_datum(c, xd)
45 * 0 will be returned, if success. An negative return value means recoverable error, and
48 * do_load_xattr_datum(c, xd)
51 * load_xattr_datum(c, xd)
53 * If xd need to call do_verify_xattr_datum() at first, it's called before calling
55 * save_xattr_datum(c, xd)
56 * is used to write xdatum to medium. xd->version will be incremented.
[all …]
Dmalloc.c38 0, 0, NULL); in jffs2_create_slab_caches()
44 0, SLAB_HWCACHE_ALIGN, NULL); in jffs2_create_slab_caches()
50 0, SLAB_HWCACHE_ALIGN, NULL); in jffs2_create_slab_caches()
56 0, 0, NULL); in jffs2_create_slab_caches()
62 0, 0, NULL); in jffs2_create_slab_caches()
68 0, 0, NULL); in jffs2_create_slab_caches()
74 0, 0, NULL); in jffs2_create_slab_caches()
81 0, 0, NULL); in jffs2_create_slab_caches()
87 0, 0, NULL); in jffs2_create_slab_caches()
92 return 0; in jffs2_create_slab_caches()
[all …]
/Linux-v6.1/drivers/dma/
Duniphier-xdmac.c20 #define XDMAC_CH_WIDTH 0x100
22 #define XDMAC_TFA 0x08
24 #define XDMAC_TFA_MASK GENMASK(5, 0)
25 #define XDMAC_SADM 0x10
29 #define XDMAC_SADM_SAM_INC 0
30 #define XDMAC_DADM 0x14
35 #define XDMAC_EXSAD 0x18
36 #define XDMAC_EXDAD 0x1c
37 #define XDMAC_SAD 0x20
38 #define XDMAC_DAD 0x24
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/Linux-v6.1/arch/powerpc/sysdev/xive/
Dcommon.c43 #define DBG_VERBOSE(fmt...) do { } while(0)
92 static bool xive_is_store_eoi(struct xive_irq_data *xd) in xive_is_store_eoi() argument
94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi; in xive_is_store_eoi()
99 * or 0 if there is no new entry.
108 return 0; in xive_read_eq()
113 return 0; in xive_read_eq()
121 if (q->idx == 0) in xive_read_eq()
125 return cur & 0x7fffffff; in xive_read_eq()
135 * (0xff if none) and return what was found (0 if none).
153 u32 irq = 0; in xive_scan_interrupts()
[all …]
/Linux-v6.1/drivers/net/
Dthunderbolt.c34 #define TBNET_E2E BIT(0)
47 #define TBNET_L0_PORT_NUM(route) ((route) & GENMASK(5, 0))
58 * supported then @frame_id is filled, otherwise it stays %0.
90 #define TBIP_HDR_LENGTH_MASK GENMASK(5, 0)
149 * @xd: XDomain the service blongs to
180 struct tb_xdomain *xd; member
204 UUID_INIT(0xc66189ca, 0x1cce, 0x4195,
205 0xbd, 0xb8, 0x49, 0x59, 0x2e, 0x5f, 0x5a, 0x4f);
209 UUID_INIT(0x798f589e, 0x3616, 0x8a47,
210 0x97, 0xc6, 0x56, 0x64, 0xa9, 0x20, 0xc8, 0xdd);
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_3_0_1_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_3_0_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_3_0_2_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_2_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/Linux-v6.1/include/linux/
Dthunderbolt.h113 TB_PROPERTY_TYPE_UNKNOWN = 0x00,
114 TB_PROPERTY_TYPE_DIRECTORY = 0x44,
115 TB_PROPERTY_TYPE_DATA = 0x64,
116 TB_PROPERTY_TYPE_TEXT = 0x74,
117 TB_PROPERTY_TYPE_VALUE = 0x76,
260 int tb_xdomain_lane_bonding_enable(struct tb_xdomain *xd);
261 void tb_xdomain_lane_bonding_disable(struct tb_xdomain *xd);
262 int tb_xdomain_alloc_in_hopid(struct tb_xdomain *xd, int hopid);
263 void tb_xdomain_release_in_hopid(struct tb_xdomain *xd, int hopid);
264 int tb_xdomain_alloc_out_hopid(struct tb_xdomain *xd, int hopid);
[all …]
/Linux-v6.1/drivers/mtd/nand/raw/
Dsm_common.c4 * Common routines & support for xD format
21 return 0; in oob_sm_ooblayout_ecc()
28 case 0: in oob_sm_ooblayout_free()
30 oobregion->offset = 0; in oob_sm_ooblayout_free()
47 return 0; in oob_sm_ooblayout_free()
68 oobregion->offset = 0; in oob_sm_small_ooblayout_ecc()
70 return 0; in oob_sm_small_ooblayout_ecc()
77 case 0: in oob_sm_small_ooblayout_free()
91 return 0; in oob_sm_small_ooblayout_free()
107 oob.block_status = 0x0F; in sm_block_markbad()
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_3_1_4_sh_mask.h33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1
35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3
37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7
39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9
41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa
42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb
[all …]
Ddpcs_4_2_2_sh_mask.h14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
Ddpcs_4_2_0_sh_mask.h27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/Linux-v6.1/tools/arch/x86/kcpuid/
Dcpuid.csv5 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs
8 1, 0, EAX, 3:0, stepping, Stepping ID
9 1, 0, EAX, 7:4, model, Model
10 1, 0, EAX, 11:8, family, Family ID
11 1, 0, EAX, 13:12, processor, Processor Type
12 1, 0, EAX, 19:16, model_ext, Extended Model ID
13 1, 0, EAX, 27:20, family_ext, Extended Family ID
15 1, 0, EBX, 7:0, brand, Brand Index
16 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
17 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
[all …]
/Linux-v6.1/sound/pci/au88x0/
Dau88x0_wt.h12 /* WT channels are grouped in banks. Each bank has 0x20 channels. */
13 /* Bank register address boundary is 0x8000 */
15 #define NR_WT_PB 0x20
18 #define WT_BAR(x) (((x)&0xffe0)<<0x8)
21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */
22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */
23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */
24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */
25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */
26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/Linux-v6.1/drivers/scsi/
Dqlogicfas408.h10 again, 0 tends to be slower, but more stable. */
25 #define QL_RESET_AT_START 0
48 /* offset 0xc */
51 #define FASTSCSI 0
54 #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/
69 If this is 0, the bus will only transfer asynchronously */
70 #define SYNCOFFST 0
83 int int_type; /* type of irq, 2 for ISA board, 0 for PCMCIA */
91 #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))
92 #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd …
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]
/Linux-v6.1/arch/powerpc/kvm/
Dbook3s_xive.c33 #define __x_eoi_page(xd) ((void __iomem *)((xd)->eoi_mmio)) argument
34 #define __x_trig_page(xd) ((void __iomem *)((xd)->trig_mmio)) argument
63 cppr = ack & 0xff; in xive_vm_ack_pending()
80 static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset) in xive_vm_esb_load() argument
84 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_esb_load()
87 val = __raw_readq(__x_eoi_page(xd) + offset); in xive_vm_esb_load()
95 static void xive_vm_source_eoi(u32 hw_irq, struct xive_irq_data *xd) in xive_vm_source_eoi() argument
98 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_source_eoi()
99 __raw_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in xive_vm_source_eoi()
100 else if (xd->flags & XIVE_IRQ_FLAG_LSI) { in xive_vm_source_eoi()
[all …]

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