Searched +full:0 +full:x92400000 (Results 1 – 5 of 5) sorted by relevance
155 reg = <0x596e8000 0x88000>;165 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;171 reg = <0x92400000 0x1000000>;175 reg = <0x942f0000 0x8000>;179 reg = <0x942f8000 0x8000>;184 reg = <0x94300000 0x100000>;190 reg = <0x3b6e8000 0x88000>;199 mboxes = <&mu2 0 0>,200 <&mu2 1 0>,201 <&mu2 3 0>;
35 #size-cells = <0>;38 A35_0: cpu@0 {41 reg = <0x0 0x0>;52 reg = <0x0 0x1>;85 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */86 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */98 reg = <0 0x92400000 0 0x2000000>;118 mboxes = <&lsio_mu1 0 0119 &lsio_mu1 1 0146 reg = <0x2c4 6>;[all …]
56 #size-cells = <0>;59 A35_0: cpu@0 {62 reg = <0x0 0x0>;64 i-cache-size = <0x8000>;67 d-cache-size = <0x8000>;79 reg = <0x0 0x1>;81 i-cache-size = <0x8000>;84 d-cache-size = <0x8000>;96 reg = <0x0 0x2>;98 i-cache-size = <0x8000>;[all …]
48 #size-cells = <0>;50 A53_0: cpu@0 {53 reg = <0x0>;57 i-cache-size = <0x8000>;60 d-cache-size = <0x8000>;73 reg = <0x1>;77 i-cache-size = <0x8000>;80 d-cache-size = <0x8000>;91 reg = <0x2>;95 i-cache-size = <0x8000>;[all …]
23 #clock-cells = <0>;27 pinctrl-0 = <&divclk1_default>;32 #clock-cells = <0>;37 pinctrl-0 = <&divclk4_pin_a>;66 pinctrl-0 = <&irled_default>;71 reg = <0x0 0x88800000 0x0 0x1400000>;75 /* This platform has all PIL regions offset by 0x1400000 */78 reg = <0x0 0x89c00000 0x0 0x6200000>;84 reg = <0x0 0x8fe00000 0x0 0x1b00000>;90 reg = <0x0 0x91900000 0x0 0xa00000>;[all …]
