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/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_dmc_regs.h12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
14 #define _PIPEDMC_CONTROL_A 0x45250
15 #define _PIPEDMC_CONTROL_B 0x45254
19 #define PIPEDMC_ENABLE REG_BIT(0)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
24 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
25 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
30 0x400 * ((dmc_id) - 1))
32 #define __DMC_REG_MMIO_BASE 0x8f000
43 #define _DMC_EVT_HTP_0 0x8f004
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/display/msm/
Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
Dqcom,sc7280-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
Dqcom,sdm845-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
73 interrupts = <0>;
79 #size-cells = <0>;
81 port@0 {
82 reg = <0>;
Dqcom,sm8150-dpu.yaml54 reg = <0x0ae01000 0x8f000>,
55 <0x0aeb0000 0x2008>;
71 interrupts = <0>;
75 #size-cells = <0>;
77 port@0 {
78 reg = <0>;
Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
Dqcom,sm8250-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
78 interrupts = <0>;
82 #size-cells = <0>;
84 port@0 {
85 reg = <0>;
Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
Dqcom,sm8350-dpu.yaml58 reg = <0x0ae01000 0x8f000>,
59 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
86 #size-cells = <0>;
88 port@0 {
89 reg = <0>;
Dqcom,sm8550-dpu.yaml64 reg = <0x0ae01000 0x8f000>,
65 <0x0aeb0000 0x2008>;
88 interrupts = <0>;
92 #size-cells = <0>;
94 port@0 {
95 reg = <0>;
Dqcom,sc8280xp-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
87 interrupts = <0>;
91 #size-cells = <0>;
93 port@0 {
94 reg = <0>;
Dqcom,sm8450-dpu.yaml65 reg = <0x0ae01000 0x8f000>,
66 <0x0aeb0000 0x2008>;
89 interrupts = <0>;
93 #size-cells = <0>;
95 port@0 {
96 reg = <0>;
Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
41 "^displayport-controller@[0-9a-f]+$":
61 reg = <0x0ae00000 0x1000>;
79 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
80 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
83 iommus = <&apps_smmu 0x1000 0x402>;
91 reg = <0x0ae01000 0x8f000>,
92 <0x0aeb0000 0x2008>;
115 interrupts = <0>;
119 #size-cells = <0>;
[all …]
Dqcom,qcm2290-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
81 reg = <0x05e00000 0x1000>;
96 iommus = <&apps_smmu 0x420 0x2>,
97 <&apps_smmu 0x421 0x0>;
102 reg = <0x05e01000 0x8f000>,
103 <0x05eb0000 0x2008>;
117 interrupts = <0>;
121 #size-cells = <0>;
[all …]
Dqcom,sm6115-mdss.yaml33 "^display-controller@[0-9a-f]+$":
39 "^dsi@[0-9a-f]+$":
51 "^phy@[0-9a-f]+$":
74 reg = <0x05e00000 0x1000>;
85 iommus = <&apps_smmu 0x420 0x2>,
86 <&apps_smmu 0x421 0x0>;
91 reg = <0x05e01000 0x8f000>,
92 <0x05eb0000 0x2008>;
107 interrupts = <0>;
111 #size-cells = <0>;
[all …]
Dqcom,sm6350-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x0ae00000 0x1000>;
90 iommus = <&apps_smmu 0x800 0x2>;
97 reg = <0x0ae01000 0x8f000>,
98 <0x0aeb0000 0x2008>;
120 interrupts = <0>;
126 #size-cells = <0>;
128 port@0 {
[all …]
Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
61 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
88 reg = <0x0ae00000 0x1000>;
91 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
92 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
104 iommus = <&apps_smmu 0x820 0x402>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
[all …]
Dqcom,msm8998-mdss.yaml39 "^display-controller@[0-9a-f]+$":
45 "^dsi@[0-9a-f]+$":
53 "^phy@[0-9a-f]+$":
73 reg = <0x0c900000 0x1000>;
87 iommus = <&mmss_smmu 0>;
94 reg = <0x0c901000 0x8f000>,
95 <0x0c9a8e00 0xf0>,
96 <0x0c9b0000 0x2008>,
97 <0x0c9b8000 0x1040>;
108 interrupts = <0>;
[all …]
Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
98 iommus = <&apps_smmu 0x880 0x8>,
99 <&apps_smmu 0xc80 0x8>;
104 reg = <0x0ae01000 0x8f000>,
105 <0x0aeb0000 0x2008>;
116 interrupts = <0>;
[all …]
Dqcom,sc7180-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
89 reg = <0xae00000 0x1000>;
104 iommus = <&apps_smmu 0x800 0x2>;
109 reg = <0x0ae01000 0x8f000>,
110 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
130 #size-cells = <0>;
[all …]
Dqcom,sm8550-mdss.yaml39 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
86 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
87 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
104 iommus = <&apps_smmu 0x1c00 0x2>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
[all …]
Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
54 "^dsi@[0-9a-f]+$":
62 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
100 iommus = <&apps_smmu 0x800 0x420>;
108 reg = <0x0ae01000 0x8f000>,
109 <0x0aeb0000 0x2008>;
125 interrupts = <0>;
129 #size-cells = <0>;
131 port@0 {
[all …]
Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
102 iommus = <&apps_smmu 0x820 0x402>;
110 reg = <0x0ae01000 0x8f000>,
111 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
133 port@0 {
[all …]
Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
86 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
87 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
104 iommus = <&apps_smmu 0x2800 0x402>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
[all …]

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