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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dqoriq-fman3-0-1g-0.dtsi3 * QorIQ FMan v3 1g port #0 device tree
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
17 cell-index = <0x28>;
19 reg = <0xa8000 0x1000>;
23 cell-index = <0>;
25 reg = <0xe0000 0x1000>;
33 #size-cells = <0>;
35 reg = <0xe1000 0x1000>;
37 pcsphy0: ethernet-phy@0 {
[all …]
Dimx8-ss-audio.dtsi14 ranges = <0x59000000 0x0 0x59000000 0x1000000>;
18 #clock-cells = <0>;
25 reg = <0x59580000 0x10000>;
40 reg = <0x59590000 0x10000>;
50 reg = <0x596e8000 0x88000>;
61 mboxes = <&lsio_mu13 2 0>,
63 <&lsio_mu13 3 0>,
Dimx8mp.dtsi45 #size-cells = <0>;
47 A53_0: cpu@0 {
50 reg = <0x0>;
61 reg = <0x1>;
72 reg = <0x2>;
83 reg = <0x3>;
98 #clock-cells = <0>;
105 #clock-cells = <0>;
112 #clock-cells = <0>;
119 #clock-cells = <0>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
Dnuvoton-common-npcm7xx.dtsi17 #clock-cells = <0>;
25 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
56 #clock-cells = <0>;
66 ranges = <0x0 0xf0000000 0x00900000>;
70 reg = <0x3fe000 0x1000>;
75 reg = <0x3fc000 0x1000>;
87 reg = <0x3ff000 0x1000>,
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/dsp/
Dfsl,dsp.yaml81 reg = <0x596e8000 0x88000>;
91 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dqoriq-fman-0-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1120 0xee0>;
62 interrupts = <100 2 0 0>;
[all …]
Dqoriq-fman3-0-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1000 0x1000>;
64 pcsphy0: ethernet-phy@0 {
[all …]
Dqoriq-fman3-1-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1000 0x1000>;
64 pcsphy8: ethernet-phy@0 {
[all …]
Dqoriq-fman-1-1g-0.dtsi2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe1120 0xee0>;
64 reg = <0x8>;
Dqoriq-fman3-0-10g-0-best-effort.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
45 cell-index = <0x28>;
47 reg = <0xa8000 0x1000>;
53 cell-index = <0>;
55 reg = <0xe0000 0x1000>;
63 #size-cells = <0>;
65 reg = <0xe1000 0x1000>;
68 pcsphy0: ethernet-phy@0 {
[all …]
Dp1023si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
54 interrupts = <19 2 0 0>,
55 <16 2 0 0>;
58 /* controller at 0xa000 */
64 bus-range = <0x0 0xff>;
66 interrupts = <16 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
[all …]
Dmpc8560ads.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x0 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
58 ecm-law@0 {
60 reg = <0x0 0x1000>;
66 reg = <0x1000 0x1000>;
[all …]
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/Linux-v5.15/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mailbox/
Darm,mhuv2.yaml74 version MHUv2.0, but the later versions do have it.
96 The first field of a tuple signifies the transfer protocol, 0 is reserved
114 arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
126 - enum: [ 0, 1 ]
127 - minimum: 0
136 relevant in doorbell protocol, should be 0 otherwise) represents the
142 mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
144 mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
145 mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
146 mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dksi8560.dts31 #size-cells = <0>;
33 PowerPC,8560@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */
49 reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
56 ranges = <0x00000000 0xfdf00000 0x00100000>;
[all …]
Dtqm8560.dts28 #size-cells = <0>;
30 PowerPC,8560@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dgcc-sdx55.c34 { 249600000, 2000000000, 0 },
38 .offset = 0x0,
43 .enable_reg = 0x6d000,
44 .enable_mask = BIT(0),
57 { 0x0, 1 },
58 { 0x1, 2 },
59 { 0x3, 4 },
60 { 0x7, 8 },
65 .offset = 0x0,
82 .offset = 0x76000,
[all …]
Dgcc-msm8998.c39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
[all …]
/Linux-v5.15/drivers/infiniband/hw/qib/
Dqib_7220_regs.h37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]

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