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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Drockchip-dw-pcie.yaml104 reg = <0x3 0xc0800000 0x0 0x390000>,
105 <0x0 0xfe280000 0x0 0x10000>,
106 <0x3 0x80000000 0x0 0x100000>;
108 bus-range = <0x20 0x2f>;
118 msi-map = <0x2000 &its 0x2000 0x1000>;
123 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
124 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsm6350.dtsi25 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
175 #size-cells = <0>;
177 CPU0: cpu@0 {
180 reg = <0x0 0x0>;
186 qcom,freq-domain = <&cpufreq_hw 0>;
201 reg = <0x0 0x100>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x200>;
225 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi30 #clock-cells = <0>;
38 #clock-cells = <0>;
41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
44 #clock-cells = <0>;
50 #clock-cells = <0>;
53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
56 #clock-cells = <0>;
62 #size-cells = <0>;
64 CPU0: cpu@0 {
67 reg = <0x0 0x0>;
[all …]
Dsm8450.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x100>;
71 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi61 #clock-cells = <0>;
67 #clock-cells = <0>;
77 reg = <0x0 0x80000000 0x0 0x600000>;
82 reg = <0x0 0x80600000 0x0 0x200000>;
87 reg = <0x0 0x80800000 0x0 0x20000>;
92 reg = <0x0 0x80820000 0x0 0x20000>;
98 reg = <0x0 0x808ff000 0x0 0x1000>;
103 reg = <0x0 0x80900000 0x0 0x200000>;
108 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0 0x8b700000 0 0x10000>;
[all …]
Dsc7280.dtsi77 #clock-cells = <0>;
83 #clock-cells = <0>;
94 reg = <0x0 0x004cd000 0x0 0x1000>;
98 reg = <0x0 0x80000000 0x0 0x600000>;
103 reg = <0x0 0x80600000 0x0 0x200000>;
108 reg = <0x0 0x80800000 0x0 0x60000>;
113 reg = <0x0 0x80860000 0x0 0x20000>;
119 reg = <0x0 0x80884000 0x0 0x10000>;
124 reg = <0x0 0x808ff000 0x0 0x1000>;
129 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
123 reg = <0x0 0x100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
144 reg = <0x0 0x200>;
151 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]