| /Linux-v6.1/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,msm8974.yaml | 56 reg = <0xfc380000 0x6a000>;
|
| /Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_catalog.c | 70 #define MERGE_3D_SM8150_MASK (0)
76 #define INTF_SDM845_MASK (0)
268 .max_mixer_blendstages = 0x7,
284 .max_mixer_blendstages = 0x4,
295 .max_mixer_blendstages = 0xb,
311 .max_mixer_blendstages = 0x9,
323 .max_mixer_blendstages = 0xb,
339 .max_mixer_blendstages = 0xb,
355 .max_mixer_blendstages = 0xb,
369 .max_mixer_blendstages = 0x7,
[all …]
|
| D | dpu_hw_interrupts.c | 20 #define MDP_SSPP_TOP0_OFF 0x0
21 #define MDP_INTF_0_OFF 0x6A000
22 #define MDP_INTF_1_OFF 0x6A800
23 #define MDP_INTF_2_OFF 0x6B000
24 #define MDP_INTF_3_OFF 0x6B800
25 #define MDP_INTF_4_OFF 0x6C000
26 #define MDP_INTF_5_OFF 0x6C800
27 #define MDP_AD4_0_OFF 0x7C000
28 #define MDP_AD4_1_OFF 0x7D000
29 #define MDP_AD4_INTR_EN_OFF 0x41c
[all …]
|
| /Linux-v6.1/drivers/rapidio/devices/ |
| D | tsi721.h | 13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | qcom-msm8974.dtsi | 20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
107 reg = <0x0 0x0>;
112 interrupts = <GIC_PPI 7 0xf04>;
121 reg = <0x08000000 0x5100000>;
126 reg = <0x0d100000 0x100000>;
[all …]
|
| D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
|
| D | omap4-l4.dtsi | 2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
|
| D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
|
| /Linux-v6.1/drivers/clk/qcom/ |
| D | gcc-sc7180.c | 37 .offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
[all …]
|
| D | gcc-sdm660.c | 54 .offset = 0x0,
57 .enable_reg = 0x52000,
58 .enable_mask = BIT(0),
84 .offset = 0x00000,
97 .offset = 0x1000,
100 .enable_reg = 0x52000,
127 .offset = 0x1000,
140 .offset = 0x77000,
143 .enable_reg = 0x52000,
157 .offset = 0x77000,
[all …]
|
| D | gcc-msm8998.c | 29 { 250000000, 2000000000, 0 },
34 .offset = 0x0,
39 .enable_reg = 0x52000,
40 .enable_mask = BIT(0),
53 .offset = 0x0,
66 .offset = 0x0,
79 .offset = 0x0,
92 .offset = 0x0,
105 .offset = 0x1000,
110 .enable_reg = 0x52000,
[all …]
|
| D | gcc-msm8916.c | 46 .l_reg = 0x21004,
47 .m_reg = 0x21008,
48 .n_reg = 0x2100c,
49 .config_reg = 0x21010,
50 .mode_reg = 0x21000,
51 .status_reg = 0x2101c,
64 .enable_reg = 0x45000,
65 .enable_mask = BIT(0),
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
[all …]
|
| D | gcc-sm8250.c | 36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]
|
| D | gcc-sc7280.c | 44 .offset = 0x0,
47 .enable_reg = 0x52010,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 { 0x3, 3 },
88 .offset = 0x0,
105 .offset = 0x1000,
108 .enable_reg = 0x52010,
122 .offset = 0x1e000,
[all …]
|
| D | gcc-sdm845.c | 39 .offset = 0x0,
42 .enable_reg = 0x52000,
43 .enable_mask = BIT(0),
56 .offset = 0x76000,
59 .enable_reg = 0x52000,
73 .offset = 0x13000,
76 .enable_reg = 0x52000,
90 { 0x0, 1 },
91 { 0x1, 2 },
92 { 0x3, 4 },
[all …]
|
| D | gcc-sm8150.c | 38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x1a000,
84 .enable_reg = 0x52000,
[all …]
|
| D | gcc-msm8996.c | 50 .offset = 0x00000,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
80 .offset = 0x00000,
95 .enable_reg = 0x5200c,
96 .enable_mask = BIT(0),
112 .enable_reg = 0x5200c,
127 .offset = 0x77000,
130 .enable_reg = 0x52000,
144 .offset = 0x77000,
[all …]
|
| D | gcc-sm8350.c | 44 .offset = 0x0,
47 .enable_reg = 0x52018,
48 .enable_mask = BIT(0),
61 { 0x1, 2 },
66 .offset = 0x0,
83 .offset = 0x76000,
86 .enable_reg = 0x52018,
101 .offset = 0x1c000,
104 .enable_reg = 0x52018,
119 { P_BI_TCXO, 0 },
[all …]
|
| D | gcc-msm8939.c | 54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
|
| D | gcc-ipq8074.c | 59 { P_XO, 0 },
65 { P_XO, 0 },
77 { P_XO, 0 },
90 { P_XO, 0 },
103 { P_XO, 0 },
116 { P_XO, 0 },
127 { P_USB3PHY_0_PIPE, 0 },
137 { P_USB3PHY_1_PIPE, 0 },
147 { P_PCIE20_PHY0_PIPE, 0 },
157 { P_PCIE20_PHY1_PIPE, 0 },
[all …]
|
| D | gcc-sc8180x.c | 44 { 249600000, 2000000000, 0 },
48 .offset = 0x0,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
67 { 0x0, 1 },
68 { 0x1, 2 },
69 { 0x3, 4 },
70 { 0x7, 8 },
75 .offset = 0x0,
90 .offset = 0x1000,
[all …]
|
| D | gcc-ipq6018.c | 53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
83 .offset = 0x21000,
103 { P_XO, 0 },
109 .offset = 0x25000,
113 .enable_reg = 0x0b000,
127 .offset = 0x25000,
141 .offset = 0x37000,
144 .enable_reg = 0x0b000,
[all …]
|
| D | gcc-sc8280xp.c | 112 .offset = 0x0,
115 .enable_reg = 0x52028,
116 .enable_mask = BIT(0),
127 { 0x1, 2 },
132 .offset = 0x0,
149 .offset = 0x2000,
152 .enable_reg = 0x52028,
164 .offset = 0x76000,
167 .enable_reg = 0x52028,
179 .offset = 0x1a000,
[all …]
|
| /Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_1_7_offset.h | 29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
|
