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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dcdns,usb3.yaml91 reg = <0x00 0x6000000 0x00 0x10000>,
92 <0x00 0x6010000 0x00 0x10000>,
93 <0x00 0x6020000 0x00 0x10000>;
Dti,j721e-usb.yaml45 If present, it restricts the controller to USB2.0 mode of
94 reg = <0x00 0x4104000 0x00 0x100>;
105 reg = <0x00 0x6000000 0x00 0x10000>,
106 <0x00 0x6010000 0x00 0x10000>,
107 <0x00 0x6020000 0x00 0x10000>;
109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
111 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
61 interrupts = <1 9 0x4>;
66 reg = <0x0 0x6020000 0 0x20000>;
[all …]
Dfsl-lx2160a.dtsi12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
[all …]
Dk3-j721e-main.dtsi14 #clock-cells = <0>;
16 clock-frequency = <0>;
20 #clock-cells = <0>;
22 clock-frequency = <0>;
29 reg = <0x0 0x70000000 0x0 0x800000>;
32 ranges = <0x0 0x0 0x70000000 0x800000>;
34 atf-sram@0 {
35 reg = <0x0 0x20000>;
41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
44 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]