Searched +full:0 +full:x58003000 (Results 1 – 10 of 10) sorted by relevance
65 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;68 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,69 <&mdma1 22 0x10 0x100008 0x0 0x0>;75 #size-cells = <0>;77 flash@0 {79 reg = <0>;
22 led-controller-0 {25 led-0 {47 #size-cells = <0>;65 pinctrl-0 = <ðernet0_rmii_pins_a>;104 pinctrl-0 = <&qspi_clk_pins_a110 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;112 #size-cells = <0>;115 flash@0 {117 reg = <0>;139 pinctrl-0 = <&sdmmc1_b4_pins_a>;[all …]
20 reg = <0xc0000000 0x40000000>;30 reg = <0x10000000 0x40000>;36 reg = <0x10040000 0x1000>;42 reg = <0x10041000 0x1000>;48 reg = <0x10042000 0x4000>;54 reg = <0x30000000 0x40000>;60 reg = <0x38000000 0x10000>;76 pinctrl-0 = <&i2c4_pins_a>;85 reg = <0x33>;86 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;[all …]
28 #clock-cells = <0>;36 pinctrl-0 = <&joystick_pins>;38 button-0 {42 interrupts = <0 IRQ_TYPE_EDGE_RISING>;80 pinctrl-0 = <&cec_pins_a>;87 pinctrl-0 = <&dcmi_pins_a>;95 hsync-active = <0>;96 vsync-active = <0>;104 #size-cells = <0>;107 panel@0 {[all …]
28 reg = <0xc0000000 0x20000000>;38 reg = <0x10000000 0x40000>;44 reg = <0x10040000 0x2000>;50 reg = <0x10042000 0x2000>;56 reg = <0x10044000 0x4000>;62 reg = <0x30000000 0x40000>;68 reg = <0x38000000 0x10000>;75 led-0 {97 adc1: adc@0 {99 pinctrl-0 = <&adc1_in6_pins_a>;[all …]
21 reg = <0xC0000000 0x40000000>;31 reg = <0x10000000 0x40000>;37 reg = <0x10040000 0x1000>;43 reg = <0x10041000 0x1000>;49 reg = <0x10042000 0x4000>;55 reg = <0x30000000 0x40000>;61 reg = <0x38000000 0x10000>;86 channel@0 {87 reg = <0>;105 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;[all …]
54 #clock-cells = <0>;56 clock-frequency = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;68 clock-frequency = <0>;75 reg = <0x40000c00 0x400>;82 #size-cells = <0>;84 reg = <0x40002400 0x400>;95 trigger@0 {97 reg = <0>;[all …]
16 #size-cells = <0>;18 cpu0: cpu@0 {21 reg = <0>;43 #size-cells = <0>;44 linaro,optee-channel-id = <0>;47 reg = <0x14>;52 reg = <0x16>;57 reg = <0x17>;61 #size-cells = <0>;63 scmi_reg11: regulator@0 {[all …]
16 #size-cells = <0>;18 cpu0: cpu@0 {22 reg = <0>;42 reg = <0xa0021000 0x1000>,43 <0xa0022000 0x2000>;57 #clock-cells = <0>;63 #clock-cells = <0>;69 #clock-cells = <0>;75 #clock-cells = <0>;81 #clock-cells = <0>;[all …]
30 #define DIS_SGX BIT(0)167 writew_relaxed(value & 0xffff, ddata->module_va + offset); in sysc_write()170 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_write()191 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_read()213 if (offset < 0) in sysc_read_revision()214 return 0; in sysc_read_revision()223 if (offset < 0) in sysc_read_sysconfig()224 return 0; in sysc_read_sysconfig()233 if (offset < 0) in sysc_read_sysstatus()234 return 0; in sysc_read_sysstatus()[all …]
